EPM3064ATC1007N

Manufacturer Part NumberEPM3064ATC1007N
DescriptionTQFP-100
ManufacturerAltera Corporation
EPM3064ATC1007N datasheet
 

Specifications of EPM3064ATC1007N

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June 2006, ver. 3.5
Features...
Table 1. MAX 3000A Device Features
Feature
EPM3032A
Usable gates
600
Macrocells
32
Logic array blocks
2
Maximum user I/O
34
pins
t
(ns)
4.5
PD
t
(ns)
2.9
SU
t
(ns)
3.0
CO1
f
(MHz)
227.3
CNT
Altera Corporation
DS-MAX3000A-3.5
®
High–performance, low–cost CMOS EEPROM–based programmable
logic devices (PLDs) built on a MAX
3.3-V in-system programmability (ISP) through the built–in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
ISP circuitry compliant with IEEE Std. 1532
Built–in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1-1990
Enhanced ISP features:
Enhanced ISP algorithm for faster programming
ISP_Done bit to ensure complete programming
Pull-up resistor on I/O pins during in–system programming
High–density PLDs ranging from 600 to 10,000 usable gates
4.5–ns pin–to–pin logic delays with counter frequencies of up to
227.3 MHz
TM
MultiVolt
I/O interface enabling the device core to run at 3.3 V,
while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic
levels
Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier
TM
(PLCC), and FineLine BGA
Hot–socketing support
Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performance
Industrial temperature range
EPM3064A
EPM3128A
1,250
2,500
64
128
4
8
66
98
4.5
5.0
2.8
3.3
3.1
3.4
222.2
192.3
MAX 3000A
Programmable Logic
Device Family
Data Sheet
®
architecture (see
Table
packages
EPM3256A
EPM3512A
5,000
10,000
256
512
16
161
208
7.5
7.5
5.2
5.6
4.8
4.7
126.6
116.3
1)
32
1