EPM3064ATC4410N Altera Corporation, EPM3064ATC4410N Datasheet

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EPM3064ATC4410N

Manufacturer Part Number
EPM3064ATC4410N
Description
TQFP
Manufacturer
Altera Corporation
Datasheet

Specifications of EPM3064ATC4410N

Date_code
10+
Features...
Altera Corporation
DS-MAX3000A-3.5
June 2006, ver. 3.5
Usable gates
Macrocells
Logic array blocks
Maximum user I/O
pins
t
t
t
f
PD
SU
CO1
CNT
Table 1. MAX 3000A Device Features
(ns)
(ns)
(ns)
(MHz)
Feature
EPM3032A
227.3
600
4.5
2.9
3.0
32
34
2
High–performance, low–cost CMOS EEPROM–based programmable
logic devices (PLDs) built on a MAX
3.3-V in-system programmability (ISP) through the built–in
IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with
advanced pin-locking capability
Built–in boundary-scan test (BST) circuitry compliant with
IEEE Std. 1149.1-1990
Enhanced ISP features:
High–density PLDs ranging from 600 to 10,000 usable gates
4.5–ns pin–to–pin logic delays with counter frequencies of up to
227.3 MHz
MultiVolt
while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic
levels
Pin counts ranging from 44 to 256 in a variety of thin quad flat pack
(TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier
(PLCC), and FineLine BGA
Hot–socketing support
Programmable interconnect array (PIA) continuous routing structure
for fast, predictable performance
Industrial temperature range
ISP circuitry compliant with IEEE Std. 1532
Enhanced ISP algorithm for faster programming
ISP_Done bit to ensure complete programming
Pull-up resistor on I/O pins during in–system programming
EPM3064A
®
1,250
222.2
TM
4.5
2.8
3.1
64
66
4
I/O interface enabling the device core to run at 3.3 V,
EPM3128A
2,500
192.3
128
5.0
3.3
3.4
98
TM
8
packages
®
architecture (see
Programmable Logic
EPM3256A
5,000
126.6
256
161
7.5
5.2
4.8
16
MAX 3000A
Device Family
Table
EPM3512A
Data Sheet
10,000
116.3
512
208
7.5
5.6
4.7
32
1)
1

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