ETC5057N STMicroelectronics, ETC5057N Datasheet

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ETC5057N

Manufacturer Part Number
ETC5057N
Description
DIP16
Manufacturer
STMicroelectronics
Datasheets

Specifications of ETC5057N

Date_code
04+

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DESCRIPTION
The ETC5057/ETC5054 family consists of A-law
and –law monolithic PCM CODEC/filters utilizing
the A/D and D/A conversion architecture shown in
the block diagram below, and a serial PCM inter-
face. The devices are fabricated using double-
poly CMOS process. The encode portion of each
device consists of an input gain adjust amplifier,
an active RC pre-filter which eliminates very high
frequency noise prior to entering a switched-ca-
pacitor band-pass filter that rejects signals below
200 Hz and above 3400 Hz. Also included are
auto-zero circuitry and a companding coder which
samples the filtered signal and encodes it in the
companded A-law or –law PCM format. The de-
code portion of each device consists of an ex-
panding decoder, which reconstructs the analog
signal from the companded A-law or –law code,
a low-pass filter which corrects for the sin x/x re-
sponse of the decoder output and rejects signals
above 3400 Hz and is followed by a single-ended
power amplifier capable of driving low impedance
loads. The devices require 1.536 MHz, 1.544
March 2000
This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
TEM (DEVICE) INCLUDING:
– Transmit high-pass and low-pass filtering.
– Receive low-pass filter with sin x/x correction.
– Active RC noise filters
– -law or A-law compatible COder and DECoder.
– Internal precision voltage reference.
– Serial I/O interface.
– Internal auto-zero circuitry.
(ETC5054FN, 20 PINS)
CCITT SPECIFICATIONS
mW
CALLY 3 mW
TERFACES
CUIT DENSITY
COMPLETE CODEC AND FILTERING SYS-
A-LAW 16 PINS (ETC5057FN, 20 PINS)
MEETS OR EXCEEDS ALL D3/D4 AND
LOW OPERATING POWER - TYPICALLY 60
POWER-DOWN STANDBY MODE - TYPI-
AUTOMATIC POWER-DOWN
TTL OR CMOS COMPATIBLE DIGITAL IN-
MAXIMIZES LINE INTERFACE CARD CIR-
0 to 70 C OPERATION
-LAW WITHOUT SIGNALING, 16 PINS
5V OPERATION
SERIAL INTERFACE CODEC/FILTER
MHz, or 2.048 MHz transmit and receive master
clocks, which may be asynchronous, transmit and
receive bit clocks which may vary from 64 kHz to
2.048 MHz, and transmit and receive frame sync
pulses. The timing of the frame sync pulses and
PCM data is compatible with both industry stand-
ard formats.
ORDERING NUMBERS:
ORDERING NUMBERS:
ORDERING NUMBERS:
DIP16 (Plastic)
SO16 (Wide)
ETC5057FN
ETC5054FN
ETC5057D
ETC5054D
ETC5057N
ETC5054N
PLCC20
ETC5054
ETC5057
1/18

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