GAL22V10D25LPNI Lattice Semiconductor Corp., GAL22V10D25LPNI Datasheet

GAL22V10D25LPNI

Manufacturer Part Number

GAL22V10D25LPNI

Description

DIP24

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.GAL22V10D-25LPNI.pdf (21 pages)

Specifications of GAL22V10D25LPNI

Date_code

07+

Current page: 1 of 21
Download datasheet (384Kb)

• HIGH PERFORMANCE E

• ACTIVE PULL-UPS ON ALL PINS

• COMPATIBLE WITH STANDARD 22V10 DEVICES

• 50% to 75% REDUCTION IN POWER VERSUS BIPOLAR

• E

• TEN OUTPUT LOGIC MACROCELLS

• PRELOAD AND POWER-ON RESET OF REGISTERS

• APPLICATIONS INCLUDE:

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

• LEAD-FREE PACKAGE OPTIONS

ESCRIPTION

The GAL22V10, at 4ns maximum propagation delay time, combines

a high performance CMOS process with Electrically Erasable (E

floating gate technology to provide the highest performance avail-

able of any 22V10 device on the market. CMOS circuitry allows

the GAL22V10 to consume much less power when compared to

bipolar 22V10 devices. E

erase times, providing the ability to reprogram or reconfigure the

device quickly and efficiently.

The generic architecture provides maximum design flexibility by

allowing the Output Logic Macrocell (OLMC) to be configured by

the user. The GAL22V10 is fully function/fuse map/parametric com-

patible with standard bipolar and CMOS 22V10 devices.

Unique test circuitry and reprogrammable cells allow complete AC,

DC, and functional testing during manufacture. As a result, Lat-

tice Semiconductor delivers 100% field programmability and func-

tionality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

22v10_12

Features

Description

— 4 ns Maximum Propagation Delay

— Fmax = 250 MHz

— 3.5 ns Maximum from Clock Input to Data Output

— UltraMOS

— Fully Function/Fuse-Map/Parametric Compatible

— 90mA Typical Icc on Low Power Device

— 45mA Typical Icc on Quarter Power Device

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

— Maximum Flexibility for Complex Logic Designs

— 100% Functional Testability

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

CELL TECHNOLOGY

with Bipolar and UVCMOS 22V10 Devices

Advanced CMOS Technology

technology offers high speed (<100ms)

CMOS

TECHNOLOGY

)

Functional Block Diagram

Pin Configuration

I/CLK

GAL22V10

Specifications GAL22V10

Top View

SOIC

PLCC

High Performance E

I/O/Q

Generic Array Logic™

GAL22V10

PRESET

RESET

I/CLK

GND

OLMC

December 2006

22V10

DIP

GAL

CMOS PLD

I/O/Q

Vcc

I/O/Q

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