ISPLSI1016EA125LJ44 Lattice Semiconductor Corp., ISPLSI1016EA125LJ44 Datasheet

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ISPLSI1016EA125LJ44

Manufacturer Part Number
ISPLSI1016EA125LJ44
Description
PLCC44
Manufacturer
Lattice Semiconductor Corp.
Datasheet

Specifications of ISPLSI1016EA125LJ44

Date_code
04+
Copyright © 2002 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
1016ea_02
• HIGH-DENSITY PROGRAMMABLE LOGIC
• NEW FEATURES
• HIGH-PERFORMANCE E
• IN-SYSTEM PROGRAMMABLE
• OFFERS THE EASE OF USE AND FAST SYSTEM
Features
— 2000 PLD Gates
— 32 I/O Pins, One Dedicated Input
— 96 Registers
— High-Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
— Small Logic Block Size for Random Logic
— Functionally Compatible with ispLSI 1016E
— 100% IEEE 1149.1 Boundary Scan Testable
— ispJTAG™ In-System Programmable via IEEE 1149.1
— User-Selectable 3.3V or 5V I/O Supports Mixed-
— Open-Drain Output Option
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
— Increased Manufacturing Yields, Reduced Time-to-
— Reprogram Soldered Device for Faster Prototyping
— Complete Programmable Device Can Combine Glue
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
Machines, Address Decoders, etc.
(JTAG) Test Access Port
Voltage Systems (V
f
t
Market and Improved Product Quality
Logic and Structured Designs
Minimize Switching Noise
Interconnectivity
max = 200 MHz Maximum Operating Frequency
pd = 4.5 ns Propagation Delay
CCIO
2
CMOS
Pin)
®
TECHNOLOGY
1
In-System Programmable High Density PLD
The ispLSI 1016EA is a High Density Programmable
Logic Device containing 96 Registers, 32 Universal I/O
pins, one Dedicated Input pin, two Dedicated Clock Input
pins, one Global OE input pin and a Global Routing Pool
(GRP). The GRP provides complete interconnectivity
between all of these elements. The ispLSI 1016EA fea-
tures 5V in-system programmability (ISP™) and in-system
diagnostic capabilities via an IEEE 1149.1 Test Access
Port. The ispLSI 1016EA offers non-volatile
reprogrammability of the logic, as well as the intercon-
nect to provide truly reconfigurable systems. A functional
superset of the ispLSI 1016 architecture, the ispLSI
1016EA device adds user-selectable 3.3V or 5V I/O and
open-drain output options.
The basic unit of logic on the ispLSI 1016EA device is the
Generic Logic Block (GLB). The GLBs are labeled A0,
A1...B7 (Figure 1). There are a total of 16 GLBs in the
ispLSI 1016EA device. Each GLB has 18 inputs, a
programmable AND/OR/Exclusive OR array, and four
outputs which can be configured to be either combinato-
rial or registered. Inputs to the GLB come from the GRP
and a dedicated input. All of the GLB outputs are brought
back into the GRP so that they can be connected to the
inputs of any other GLB on the device.
Functional Block Diagram
Description
A1
A2
A3
A4
A5
A6
A7
A0
ispLSI
Global Routing Pool (GRP)
Logic
Array
D Q
D Q
D Q
D Q
®
GLB
1016EA
January 2002
B 7
B 6
B 5
B 4
B 3
B 2
B 1
B 0
CLK
0139C/1016EA

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