M30626FJPFPU5C

Manufacturer Part NumberM30626FJPFPU5C
DescriptionQFP-100
ManufacturerRenesas Electronics Corporation.
M30626FJPFPU5C datasheet
 


Specifications of M30626FJPFPU5C

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Chapter 1 Overview
1.3.2 Address registers (A0 and A1)
The address registers (A0 and A1) consist of 16 bits, and have the similar functions as the data regis-
ters. These registers are used for address register-based indirect addressing and address register-
based relative addressing.
For some instructions, registers A1 and A0 can be combined to configure a 32-bit address register
(A1A0).
1.3.3 Frame base register (FB)
The frame base register (FB) consists of 16 bits, and is used for FB-based relative addressing.
1.3.4 Program counter (PC)
The program counter (PC) consists of 20 bits, indicating the address of an instruction to be executed
next.
1.3.5 Interrupt table register (INTB)
The interrupt table register (INTB) consists of 20 bits, indicating the initial address of an interrupt vector
table.
1.3.6 User stack pointer (USP) and interrupt stack pointer (ISP)
There are two types of stack pointers: user stack pointer (USP) and interrupt stack pointer (ISP), each
consisting of 16 bits.
The stack pointer (USP/ISP) you want can be switched by a stack pointer select flag (U flag).
The stack pointer select flag (U flag) is bit 7 of the flag register (FLG).
1.3.7 Static base register (SB)
The static base register (SB) consists of 16 bits, and is used for SB-based relative addressing.
1.3.8 Flag register (FLG)
The flag register (FLG) consists of 11 bits, and is used as a flag, one bit for one flag. For details about
the function of each flag, see Section 1.4, “Flag Register (FLG).”
1.3 Register Configuration
5