M30626FJPFPU5C

Manufacturer Part NumberM30626FJPFPU5C
DescriptionQFP-100
ManufacturerRenesas Electronics Corporation.
M30626FJPFPU5C datasheet
 

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Chapter 5
Interrupt
5.7 Precautions for Interrupts
5.7.1 Reading address 00000
Do not read the address 00000
reads interrupt information (interrupt number and interrupt request priority level) from the address
00000
during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to “0”.
16
If the address 00000
is read in a program, the IR bit for the interrupt which has the highest priority
16
among the enabled interrupts is cleared to “0”. This causes a problem that the interrupt is canceled, or an
unexpected interrupt request is generated.
5.7.2 Setting the SP
Set any value in the SP(USP, ISP) before accepting an interrupt. The SP(USP, ISP) is cleared to ‘0000
after reset. Therefore, if an interrupt is accepted before setting any value in the SP(USP, ISP), the pro-
gram may go out of control.
_______
Especially when using NMI interrupt, set a value in the ISP at the beginning of the program. For the first
and only the first instruction after reset, all interrupts including NMI interrupt are disabled.
5.7.3 Rewrite the Interrupt Control Register
(1) The interrupt control register for any interrupt should be modified in places where no requests for that
interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register.
(2) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the
instruction to be used.
Changing any bit other than the IR bit
If while executing an instruction, a request for an interrupt controlled by the register being modified
occurs, the IR bit in the register may not be set to “1” (interrupt requested), with the result that the
interrupt request is ignored. If such a situation presents a problem, use the instructions shown below
to modify the register.
Usable instructions: AND, OR, BCLR, BSET
Changing the IR bit
Depending on the instruction used, the IR bit may not always be cleared to “0” (interrupt not re-
quested). Therefore, be sure to use the MOV instruction to clear the IR bit.
(3) When using the I flag to disable an interrupt, refer to the sample program fragments shown below as
you set the I flag. (Refer to (2) for details about rewrite the interrupt control registers in the sample
program fragments.)
Examples 1 through 3 show how to prevent the I flag from being set to “1” (interrupts enabled) before the
interrupt control register is rewrited, owing to the effects of the internal bus and the instruction queue
buffer.
16
in a program. When a maskable interrupt request is accepted, the CPU
16
262
_______
’
16

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