M30626FJPFPU5C

Manufacturer Part NumberM30626FJPFPU5C
DescriptionQFP-100
ManufacturerRenesas Electronics Corporation.
M30626FJPFPU5C datasheet
 


Specifications of M30626FJPFPU5C

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6
Instructions
JMP
TEST_11
under execution
64
Fetch code
Content at jump address is
prefetched at the same time the
instruction queue buffer is
cleared.
04
04
04
73
73
04
04
04
01
Instruction
queue buffer
04
04
04
Jump address
BCLK
Address bus
FC052
FC056
Data bus(H)
Data bus(L)
RD
WR
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
:Indicates the locations of the instruction queue buffer that are cleared.
Figure 6.1.1. When executing a register transfer instruction starting from an even address
(Program area: 16-bit bus without wait state; Data area: 16-bit bus without wait state)
Instructions
JMP
TEST_11
under execution
65
Fetch code
Not all codes are ready in
Content at jump address is
the instruction queue buffer,
prefetched at the same time
so the next read is
the instruction queue buffer
performed
is cleared.
04
04
04
73
73
04
04
04
Instruction
04
04
04
queue buffer
Jump address
BCLK
Address bus
FC0C4
FC0C9
Data bus (H)
73
Data bus (L)
P
RD
WR
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
: Indicates the locations of the instruction queue buffer that are cleared.
Figure 6.1.2. When executing a register transfer instruction starting from an odd address
(Program area: 16-bit bus without wait state; Data area: 16-bit bus without wait state)
MOV.W
JMP
TEST_12
7301
64
Content at jump address is
prefetched at the same time the
Fetch
instruction queue buffer is
Fetch
cleared.
73
73
64
04
04
73
64
04
04
F1
01
04
04
04
04
F1
00
64
04
04
04
04
04
04
40
04
04
FC058
FC05A
FC05E
FC060
04
F1
01
04
73
64
04
73
P
P
P
P
MOV.W
JMP
TEST_12
7301
64
Content at jump address is
prefetched at the same time
the instruction queue buffer is
cleared.
Fetch
Fetch
73
73
64
64
04
04
04
73
01
01
04
04
04
04
04
64
64
04
04
04
04
04
04
04
04
FC0CA
FC0CC
FC0CE
FC0D1
64
04
04
73
01
04
04
P
P
P
P
267
Calculation number of cycles
6.1 Instruction queue buffer
Sample program
Address
Code
Instruction
FC050
64
JMP
TEST_11
FC051
04
NOP
FC052
04
NOP
FC053
04
NOP
FC054
04
NOP
FC055
04
NOP
FC056
TEST_11:
FC056
7301
MOV.W
R0,R1
00
FC058
64
JMP
TEST_12
FC059
04
NOP
FC05A
04
NOP
FC05B
04
NOP
FC05C
04
NOP
40
FC05D
04
NOP
FC05E
TEST_12:
P
Not all codes are ready in the
instruction queue buffer, so the
next read is performed
73
73
F1
F1
00
00
Sample program
Address
Code
Instruction
FC0C2
65
JMP
TEST_11
FC0C3
04
NOP
FC0C4
04
NOP
FC0C5
04
NOP
FC0C6
04
NOP
FC0C7
04
NOP
FC0C8
04
NOP
FC0C9
TEST_11:
FC0C9
7301
MOV.W
R0,R1
FC0D2
FC0CB
64
JMP
TEST_12
FC0CC
04
NOP
FC0CD
04
NOP
FC0CE
04
NOP
FC0CF
04
NOP
00
FC0D0
04
NOP
FC0D1
TEST_12:
F1
P