M30626FJPFPU5C

Manufacturer Part NumberM30626FJPFPU5C
DescriptionQFP-100
ManufacturerRenesas Electronics Corporation.
M30626FJPFPU5C datasheet
 


Specifications of M30626FJPFPU5C

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6
Instructions
JMP
TEST_11
under execution
64
Fetch code
Content at jump address is
prefetched at the same time
the instruction queue buffer
is cleared.
04
04
04
73
73
04
04
04
F1
Instruction
queue buffer
04
04
04
Address from which to read data
Jump address
BCLK
Address bus
FC05A
FC05E
Data bus (H)
Data bus (L)
RD
WR
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
DR : Indicates a data read.
: Indicates the locations of the instruction queue buffer that are cleared.
Figure 6.1.3. When executing an instruction to read from even addresses starting from an even address
(Program area: 16-bit bus without wait state; Data area: 16-bit bus without wait state)
Instructions
JMP
TEST_11
under execution
64
Fetch code
Content at jump address is
prefetched at the same time
Fetch
the instruction queue buffer
is cleared.
73
04
04
04
73
73
04
04
04
F1
F1
Instruction
queue buffer
04
04
04
01
40
Low-order address from
Jump address
which to read data
BCLK
Address bus
FC064
FC068
FC06A
Data bus (H)
F1
Data bus (L)
73
P
RD
WR
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
DR : Indicates a data read.
: Indicates the locations of the instruction queue buffer that are cleared.
Figure 6.1.4. When executing an instruction to read from odd addresses starting from an even address
(Program area: 16-bit bus without wait state; Data area: 16-bit bus without wait state)
MOV.W
JMP
TEST_12
73F1
0040
64
Fetch
Fetch
Fetch
73
00
64
64
04
04
04
73
F1
40
04
04
04
04
04
F1
00
64
04
04
04
04
40
04
04
FC062
04000
FC064
FC060
FC068
Content at address 4001
16
04
F1
40
AA
04
Content at address 4000
16
04
73
00
AA
64
P
P
P
DR
P
MOV.W
JMP
TEST_12
73F1
0040
64
Read from even
address
Fetch
Fetch
00
64
64
64
04
04
04
40
04
04
04
04
04
04
64
04
04
04
04
04
04
High-order address from
which to read data
FC06C
04001
04002
FC06E
FC072
Content at address 4001
16
40
04
AA
04
Content at address 4002
16
04
00
64
AA
P
P
DR
DR
P
268
Calculation number of cycles
6.1 Instruction queue buffer
Content at jump address is
prefetched at the same time
the instruction queue buffer is
cleared.
73
F1
00
Sample program
40
Address
Code
Instruction
FC058
64
JMP
TEST_11
FC059
04
NOP
FC05A
04
NOP
FC05B
04
NOP
FC05C
04
NOP
FC05D
04
NOP
FC05E
TEST_11:
FC05E
73F10040
MOV.W
04000h, R1
FC062
64
JMP
TEST_12
FC06A
FC063
04
NOP
FC064
04
NOP
FC065
04
NOP
FC066
04
NOP
FC067
04
NOP
00
F1
FC068
TEST_12:
73
40
P
P
Content at jump address is
prefetched at the same time
the instruction queue buffer
is cleared.
73
73
F1
F1
00
Sample program
40
Address
Code
Instruction
FC062
64
JMP
FC063
04
NOP
FC064
04
NOP
FC065
04
NOP
FC066
04
NOP
FC067
04
NOP
FC068
TEST_11:
FC068
73F10140
MOV.W
FC06C
64
JMP
FC074
FC06D
04
NOP
FC06E
04
NOP
FC06F
04
NOP
FC070
04
NOP
00
F1
FC071
04
NOP
FC072
TEST_12:
73
40
P
P
TEST_11
04001h, R1
TEST_12

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