M30626FJPFPU5C

Manufacturer Part NumberM30626FJPFPU5C
DescriptionQFP-100
ManufacturerRenesas Electronics Corporation.
M30626FJPFPU5C datasheet
 


Specifications of M30626FJPFPU5C

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6
Instructions
JMP
TEST_11
under execution
Fetch code
64
Content at jump address is
prefetched at the same time
Fetch
the instruction queue buffer
is cleared.
73
04
04
04
73
73
04
04
04
FF
FF
Instruction
queue buffer
04
04
04
00
40
Jump address
Address from which to read data
BCLK
Address bus
FC06E
FC072
FC074
Data bus (H)
FF
Data bus (L)
73
P
RD
WR
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
DR : Indicates a data read.
DW : Indicates a data write.
: Indicates the locations of the instruction queue buffer that are cleared.
Figure 6.1.5. When executing an instruction to transfer data between even addresses starting from an even address
(Program area: 16-bit bus without wait state; Data area: 16-bit bus without wait state)
Instructions
JMP
TEST_11
under execution
Fetch code
64
Content at jump address is
prefetched at the same time
Fetch
the instruction queue buffer
is cleared.
73
04
04
04
73
73
04
04
04
F1
F1
Instruction
queue buffer
04
04
04
00
40
Jump address
Address from which
to read data
BCLK
Address bus
FC152
FC156
FC158
Data bus (H)
F1
Data bus (L)
73
P
RD
WR
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
DR : Indicates a data read.
DW : Indicates a data write.
: Indicates the locations of the instruction queue buffer that are cleared.
Figure 6.1.6. When executing an instruction to read from even addresses starting from an even address
(Program area: 16-bit bus without wait state; Data area: 16-bit bus with wait state)
MOV.W
JMP
TEST_12
73FF
0040
0240
64
The instruction
Content at jump address is
queue buffer is
Fetch
prefetched at the same time
Fetch
Fetch
emptied, so one
the instruction queue buffer is
more cycle is waited.
cleared.
00
02
64
64
04
04
04
40
40
04
04
04
04
04
02
04
04
04
04
40
04
Address from which to write data
04002
0FC078
FC076
04000
FC07A
Content at address 4001
16
40
40
AA
AA
04
04
Content at address 4000
16
00
02
64
AA
AA
04
P
P
DR
P
P
DW
MOV.W
JMP
TEST_12
73F1
0040
64
Content at jump address is prefetched at
the same time the instruction queue buffer
Fetch
Fetch
is cleared.
00
64
64
64
04
04
04
40
04
04
04
04
04
04
64
04
04
04
04
04
04
1 wait
FC15C
FC15A
04000
Content at address 4001
16
04
AA
04
40
Content at address 4000
16
00
64
04
AA
DR
P
P
P
269
Calculation number of cycles
6.1 Instruction queue buffer
73
73
F1
F1
00
Sample program
40
Address
Code
Instruction
FC06C
64
JMP
TEST_11
FC06D
04
NOP
FC06E
04
NOP
FC06F
04
NOP
FC070
04
NOP
FC071
04
NOP
FC072
TEST_11:
FC072
73FF00400240 MOV.W
04000h, 04002h
FC078
64
JMP
TEST_12
FC07E
FC080
FC079
04
NOP
FC07A
04
NOP
FC07B
04
NOP
FC07C
04
NOP
00
FC07D
04
NOP
F1
FC07E
TEST_12:
73
40
P
P
73
73
FF
FF
00
Sample program
40
Address
Code
Instruction
FC150
64
JMP
TEST_11
FC151
04
NOP
FC152
04
NOP
FC153
04
NOP
FC154
04
NOP
FC155
04
NOP
FC156
TEST_11:
FC156
73F10040
MOV.W 04000h, R1
FC15A
64
JMP
TEST_12
FC160
FC162
FC15B
04
NOP
FC15C
04
NOP
FC15D
04
NOP
FC15E
04
NOP
00
FF
FC15F
04
NOP
FC160
TEST_12:
73
40
P
P