M30626FJPFPU5C

Manufacturer Part NumberM30626FJPFPU5C
DescriptionQFP-100
ManufacturerRenesas Electronics Corporation.
M30626FJPFPU5C datasheet
 


Specifications of M30626FJPFPU5C

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6
Instructions
JMP
TEST_11
under execution
Fetch code
64
Content at jump address is
Fetch
prefetched at the same time
the instruction queue buffer
is cleared.
73
04
04
04
73
73
04
04
04
F1
F1
Instruction
queue buffer
04
04
04
00
40
Low-order address from
Jump address
which to read data
BCLK
Address bus
FC05A
FC05E
FC060
Data bus (H)
F1
Content at address 4000
Data bus (L)
73
P
RD
WR
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
DR : Indicates a data read.
DW : Indicates a data write.
: Indicates the locations of the instruction queue buffer that are cleared.
Figure 6.1.7. When executing a read instruction for memory connected to 8-bit bus
(Program area: 16-bit bus without wait state; Data area: 8-bit bus without wait state)
Instructions
JMP
TEST_11
under execution
64
Fetch code
Content at jump address is
prefetched at the same time
Fetch
the instruction queue buffer
is cleared.
04
04
04
73
73
04
04
04
F1
Instruction
queue buffer
04
04
04
Jump address
BCLK
Address bus
FC065
FC068
FC069
Data bus (H)
Data bus (L)
73
F1
P
P
RD
WR
P : Indicates a prefetch (reading from memory into the instruction queue buffer).
DR : Indicates a data read.
DW : Indicates a data write.
: Indicates the locations of the instruction queue buffer that are cleared.
Figure 6.1.8. When executing a read instruction for memory connected to 8-bit bus
(Program area: 8-bit bus without wait state; Data area: 8-bit bus without wait state)
MOV.W
JMP
TEST_12
73F1
0040
64
Content at jump address is prefetched
at the same time the instruction queue
Fetch
Fetch
buffer is cleared.
00
64
64
64
04
04
04
73
40
04
04
04
04
04
04
FF
64
04
04
04
04
04
04
High-order address from
which to read data
FC062
04000
FC064
FC068
04001
04
04
40
Content at address 4001
16
16
AA
00
AA
04
64
P
P
DR
DR
P
MOV.W
73F1
0040
64
Content at jump address is prefetched
at the same time the instruction queue
Fetch
Fetch
buffer is cleared.
73
00
00
00
64
64
64
04
04
F1
40
40
40
04
04
04
04
04
00
64
64
04
04
04
04
Low-order address from
High-order address from
which to read data
which to read data
FC06A
FC06B
FC06C
FC06D
04000
04001
FC06E
FC06F
Content at address 4000
Content at address 4001
16
40
04
00
64
04
AA
AA
04
P
P
P
P
DR
DR
P
P
270
Calculation number of cycles
6.1 Instruction queue buffer
73
FF
00
Sample program
40
Address
Code
Instruction
FC058
64
JMP
TEST_11
FC059
04
NOP
FC05A
04
NOP
FC05B
04
NOP
FC05C
04
NOP
FC05D
04
NOP
FC05E
TEST_11:
FC05E
73F10040
MOV.W
04000h, R1
FC062
64
JMP
TEST_12
FC06A
FC063
04
NOP
FC064
04
NOP
FC065
04
NOP
FC066
04
NOP
FC067
04
NOP
FF
00
FC068
TEST_12:
73
40
P
P
JMP
TEST_12
04
73
73
73
Sample programs
04
FF
FF
Address
Code
Instruction
FC062
64
JMP
04
00
FC063
04
NOP
FC064
04
NOP
FC065
04
NOP
FC066
04
NOP
FC067
04
NOP
FC068
TEST_11:
FC068
73F10040
MOV.W 04000h, R1
FC06C
64
JMP
FC06D
04
NOP
FC06E
04
NOP
FC06F
04
NOP
FC072
FC073
FC074
FC070
04
NOP
FC071
04
NOP
FC072
TEST_12:
16
00
73
FF
P
P
P
TEST_11
TEST_12