M30626FJPFPU5C

Manufacturer Part NumberM30626FJPFPU5C
DescriptionQFP-100
ManufacturerRenesas Electronics Corporation.
M30626FJPFPU5C datasheet
 


Specifications of M30626FJPFPU5C

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PrevNext
Chapter 3
Functions
DIVX
[ Syntax ]
DIVX.size
src
[ Operation ]
If the size specifier (.size) is (.B)
R0L (quotient), R0H (remainder)
If the size specifier (.size) is (.W)
R0 (quotient), R2 (remainder)
[ Function ]
• This instruction divides R2R0 (R0)
*1
(R0H)
. The remainder has the same sign as the divisor. Shown in ( )
when you selected (.B) for the size specifier (.size).
• If src is an A0 or A1 when the size specifier (.size) you selected is (.B), operation is performed on the
8 low-order bits of A0 or A1.
• If you specify (.B) for the size specifier (.size), the O flag is set when the operation resulted in the
quotient exceeding 8 bits or the divisor is 0. At this time, R0L and R0H are indeterminate.
• If you specify (.W) for the size specifier (.size), the O flag is set when the operation resulted in the
quotient exceeding 16 bits or the divisor is 0. At this time, R0 and R2 are indeterminate.
[ Selectable src ]
src
R0L/R0
R0H/R1
R1L/R2
A0/A0
A1/A1
[A0]
dsp:8[A0]
dsp:8[A1]
dsp:8[SB]
dsp:16[A0] dsp:16[A1]
dsp:16[SB]
dsp:20[A0] dsp:20[A1]
abs20
R2R0
R3R1
A1A0
[ Flag Change ]
U
I
O
B
S
Flag
Change
Conditions
O :
The flag is set when the operation resulted in the quotient exceeding 16 bits (.W) or 8 bits (.B) or
the divisor is 0; otherwise cleared.
[ Description Example ]
DIVX.B
A0
DIVX.B
#4
DIVX.W
R0
[ Related Instructions ]
DIV,DIVU,MUL,MULU
Singed divide
DIVide eXtension
B , W
R0
src
R2R0
src
*1
by signed src and stores the quotient in R0 (R0L)
R1H/R3
[A1]
dsp:8[FB]
abs16
#IMM
Z
D
C
;A0’s 8 low-order bits is the divisor.
69
3.2 Functions
DIVX
[ Instruction Code/Number of Cycles ]
Page= 174
*1
and the remainder in R2
*1
are the registers that are operated on