MT4C4M4E8DJ5 Micron Semiconductor Products, MT4C4M4E8DJ5 Datasheet

MT4C4M4E8DJ5

Manufacturer Part Number

MT4C4M4E8DJ5

Description

SOJ

Manufacturer

Micron Semiconductor Products

Datasheet

1.MT4C4M4E8DJ5.pdf (22 pages)

Specifications of MT4C4M4E8DJ5

Date_code

04+

Current page: 1 of 22
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DRAM

FEATURES

• Industry-standard x4 pinout, timing, functions and

• High-performance, low-power CMOS silicon-gate

• Single +3.3V ±0.3V power supply

• All inputs, outputs and clocks are TTL-compatible

• Refresh modes: RAS#-ONLY, HIDDEN and CAS#-

• Optional self refresh (S) for low-power data retention

• 11 row, 11 column addresses (2K refresh) or

• Extended Data-Out (EDO) PAGE MODE access

OPTIONS

• Refresh Addressing

• Packages

• Timing

• Refresh Rates

NOTE:

*Contact factory for availability

KEY TIMING PARAMETERS

GENERAL DESCRIPTION

memory containing 16,777,216 bits organized in a x4 con-

figuration. RAS# is used to latch the row address (first 11

bits for 2K and first 12 bits for 4K). Once the page has been

opened by RAS#, CAS# is used to latch the column address

4 Meg x 4 EDO DRAM

D47.p65 – Rev. 6/98

SPEED

The 4 Meg x 4 DRAM is a randomly accessed, solid-state

packages

process

BEFORE-RAS# (CBR)

12 row, 10 column addresses (4K refresh)

2,048 (2K) rows

4,096 (4K) rows

Plastic SOJ (300 mil)

Plastic TSOP (300 mil)

50ns access

60ns access

Standard Refresh

Self Refresh (128ms period)

-5

-6

1. The 4 Meg x 4 EDO DRAM base number differentiates the

2. The “#” symbol indicates signal is active LOW.

offerings in one place - MT4LC4M4E8. The fifth field

distinguishes various options: E8 designates a 2K refresh and E9

designates a 4K refresh for EDO DRAMs.

104ns

84ns

50ns

60ns

RAC

20ns

25ns

30ns

MARKING

13ns

15ns

CAC

None

-5

-6

10ns

8ns

CAS

MT4LC4M4E8, MT4LC4M4E9

For the latest data sheet revisions, please refer to the Micron

Web site: www.micron.com/mti/msp/html/datasheet.html

4 MEG x 4 EDO DRAM PART NUMBERS

x = speed

(the latter 11 bits for 2K and the latter 10 bits for 4K; address

pins A10 and A11 are “Don’t Care”). READ and WRITE

cycles are selected with the WE# input.

LOW on WE# dictates write mode. During a WRITE cycle,

data-in (D) is latched by the falling edge of WE# or CAS#,

whichever occurs last. An EARLY WRITE occurs when

WE# is taken LOW prior to CAS# falling. A LATE WRITE or

READ-MODIFY-WRITE occurs when WE# falls after CAS#

is taken LOW. During EARLY WRITE cycles, the data

outputs (Q) will remain High-Z regardless of the state of

OE#. During LATE WRITE or READ-MODIFY-WRITE

** NC on 2K refresh and A11 on 4K refresh options.

**NC/A11

PART NUMBER

MT4LC4M4E8DJ-x

MT4LC4M4E8DJ-x S

MT4LC4M4E8TG-x

MT4LC4M4E8TG-x S

MT4LC4M4E9DJ-x

MT4LC4M4E9DJ-x S

MT4LC4M4E9TG-x

MT4LC4M4E9TG-x S

A logic HIGH on WE# dictates read mode, while a logic

RAS#

WE#

DQ0

DQ1

A10

24/26-Pin SOJ

PIN ASSIGNMENT (Top View)

Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADDRESSING

REFRESH

DQ3

DQ2

CAS #

OE #

**NC/A11

RAS#

WE#

DQ0

DQ1

24/26-Pin TSOP

A10

PACKAGE

EDO DRAM

TSOP

SOJ

4 MEG x 4

1998, Micron Technology, Inc.

Standard

REFRESH

Self

DQ3

DQ2

CAS#

OE#

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