S3C44B0X

Manufacturer Part NumberS3C44B0X
DescriptionBGA
ManufacturerSamsung
S3C44B0X datasheets
 


Specifications of S3C44B0X

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S3C2400 RISC MICROPROCESSOR
ASSEMBLER SYNTAX
<LDC|STC>{cond}{L} p#,cd,<Address>
LDC
Load from memory to coprocessor
STC
Store from coprocessor to memory
{L}
When present perform long transfer (N=1), otherwise perform short transfer (N=0)
{cond}
Two character condition mnemonic. See Table 3-2..
p#
The unique number of the required coprocessor
cd
An expression evaluating to a valid coprocessor register number that is placed in the
CRd field
<Address>
can be:
1
An expression which generates an address:
The assembler will attempt to generate an instruction using the PC as a base and a
corrected immediate offset to address the location given by evaluating the expression.
This will be a PC relative, pre-indexed address. If the address is out of range, an error
will be generated
2
A pre-indexed addressing specification:
[Rn]
[Rn,<#expression>]{!}
3
A post-indexed addressing specification:
[Rn],<#expression
{!}
Rn
If Rn is R15, the assembler will subtract 8 from the offset value to allow for ARM920T pipelining.
EXAMPLES
LDC
p1,c2,table
STCEQL
p2,c3,[R5,#24]!
Although the address offset is expressed in bytes, the instruction offset field is in words. The assembler will
adjust the offset appropriately.
offset of zero
offset of <expression> bytes
offset of <expression> bytes
write back the base register (set the W bit) if! is present
is an expression evaluating to a valid
ARM920T register number.
NOTES
; Load c2 of coproc 1 from address
; table, using a PC relative address.
; Conditionally store c3 of coproc 2
; into an address 24 bytes up from R5,
; write this address back to R5, and use
; long transfer option (probably to store multiple words).
NOTES
ARM INSTRUCTION SET
3-55