S3C44B0X

Manufacturer Part NumberS3C44B0X
DescriptionBGA
ManufacturerSamsung
S3C44B0X datasheets
 

Specifications of S3C44B0X

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S3C2400 RISC MICROPROCESSOR
5. Overflow in unsigned multiply accumulate with a 64 bit result
UMULL
Rl,Rh,Rm,Rn
ADDS
Rl,Rl,Ra1
ADC
Rh,Rh,Ra2
BCS
overflow
6. Overflow in signed multiply accumulate with a 64 bit result
SMULL
Rl,Rh,Rm,Rn
ADDS
Rl,Rl,Ra1
ADC
Rh,Rh,Ra2
BVS
overflow
Overflow checking is not applicable to unsigned and signed multiplies with a 64-bit result, since overflow
does not occur in such calculations.
PSEUDO-RANDOM BINARY SEQUENCE GENERATOR
It is often necessary to generate (pseudo-) random numbers and the most efficient algorithms are based on shift
generators with exclusive-OR feedback rather like a cyclic redundancy check generator. Unfortunately the sequence
of a 32 bit generator needs more than one feedback tap to be maximal length (i.e. 2^32-1 cycles before repetition),
so this example uses a 33 bit register with taps at bits 33 and 20. The basic algorithm is newbit:=bit 33 eor bit 20,
shift left the 33 bit number and put in newbit at the bottom; this operation is performed for all the newbits needed (i.e.
32 bits). The entire operation can be done in 5 S cycles:
TST
Rb,Rb,LSR#1
MOVS
Rc,Ra,RRX
ADC
Rb,Rb,Rb
EOR
Rc,Rc,Ra,LSL#12
EOR
Ra,Rc,Rc,LSR#20
MULTIPLICATION BY CONSTANT USING THE BARREL SHIFTER
Multiplication by 2^n (1,2,4,8,16,32..)
MOV
Ra, Rb, LSL #n
Multiplication by 2^n+1 (3,5,9,17..)
ADD
Ra,Ra,Ra,LSL #n
Multiplication by 2^n-1 (3,7,15..)
RSB
Ra,Ra,Ra,LSL #n
; 3 to 6 cycles
; Lower accumulate
; Upper accumulate
; 1 cycle and 2 registers
; 3 to 6 cycles
; Lower accumulate
; Upper accumulate
; 1 cycle and 2 registers
NOTES
; Enter with seed in Ra (32 bits),
; Rb (1 bit in Rb lsb), uses Rc.
; Top bit into carry
; 33 bit rotate right
; Carry into lsb of Rb
; (involved!)
; (similarly involved!) new seed in Ra, Rb as before
ARM INSTRUCTION SET
3-61