S3C44B0X Samsung, S3C44B0X Datasheet - Page 152

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S3C44B0X

Manufacturer Part Number
S3C44B0X
Description
BGA
Manufacturer
Samsung
Datasheets

Specifications of S3C44B0X

Date_code
02+
S3C2400X01 RISC MICROPROCESSOR
Table 4-17. The Conditional Branch Instructions (Continued)
L
THUMB assembler
1001
BLS label
1010
BGE label
1011
BLT label
1100
BGT label
1101
BLE label
NOTES
1.
While label specifies a full 9-bit two's complement address, this must always be halfword-aligned (ie with bit 0 set to 0)
since the assembler actually places label >> 1 in field SOffset8.
2.
Cond = 1110 is undefined, and should not be used.
Cond = 1111 creates the SWI instruction: see .
INSTRUCTION CYCLE TIMES
All instructions in this format have an equivalent ARM instruction as shown in Table 3-1. The instruction cycle times
for the THUMB instruction are identical to that of the equivalent ARM instruction.
EXAMPLES
CMP R0, #45 ;
BGT over
over
ARM equivalent
BLS label
Branch if C clear or Z set (unsigned lower or
same)
BGE label
Branch if N set and V set, or N clear and V
clear (greater or equal)
BLT label
Branch if N set and V clear, or N clear and V
set (less than)
BGT label
Branch if Z clear, and either N set and V set
or N clear and V clear (greater than)
BLE label
Branch if Z set, or N set and V clear, or N
clear and V set (less than or equal)
Branch to over-if R0 > 45.
; Note that the THUMB opcode will contain
; the number of halfwords to offset.
; Must be halfword aligned.
THUMB INSTRUCTION SET
Action
4-35

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