S3C44B0X

Manufacturer Part NumberS3C44B0X
DescriptionBGA
ManufacturerSamsung
S3C44B0X datasheets
 

Specifications of S3C44B0X

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S3C2400 RISC MICROPROCESSOR
FUNCTION DESCRIPTION
BANK0 BUS WIDTH
The data bus width of BANK0 (nGCS0) should be configured as one of 8-bit,16-bit and 32-bit. Because the BANK0 is
the booting ROM bank(map to 0x0000_0000), the bus width of BANK0 should be determined before the first ROM
access, which will be determined by the logic level of OM[1:0] at Reset.
OM1 (Operating Mode 1)
0
0
1
1
Programming Memory Controller
All thirteen memory control registers have to be written using the STMIA instruction as shown in the following
example;
;Set memory control registers
ldr
r0,=SMRDATA
ldr
r1,=BWSCON
add
r2, r0, #52
0
ldr
r3, [r0], #4
str
r3, [r1], #4
cmp
r2, r0
bne
%B0
SMRDATA
DATA
DCD
0x22221210
DCD
0x00000600
DCD
0x00000700
DCD
0x00000700
DCD
0x00000700
DCD
0x00000700
DCD
0x00000700
DCD
0x0001002a
DCD
0x0001002a
DCD
0x00960000 + 953
DCD
0x0
DCD
0x20
DCD
0x20
MEMORY (SROM/DRAM/SDRAM) ADDRESS PIN CONNECTIONS
Memory Address Pin
A0
A1
OM0 (Operating Mode 0)
0
1
0
1
; BWSCON Address
; End address of SMRDATA
; BWSCON
; GCS0
; GCS1
; GCS2
; GCS3
; GCS4
; GCS5
; GCS6, EDO DRAM(Trcd=3, Tcas=2, Tcp=1, CAN=10bit)
; GCS7, EDO DRAM
; Refresh(REFEN=1, TREFMD=0, Trp=3, Trc=5, Tchr=3)
; Bank Size, 32MB/32MB
; MRSR 6(CL=2)
; MRSR 7(CL=2)
S3C2400 Address
S3C2400 Address
@ 8-bit Data Bus
@ 16-bit Data Bus
A0
A1
MEMORY CONTROLLER
Booting ROM Data width
8-bit
16-bit
32-bit
Test Mode
S3C2400 Address
@ 32-bit Data Bus
A1
A2
A2
A3
5-3