S3C44B0X

Manufacturer Part NumberS3C44B0X
DescriptionBGA
ManufacturerSamsung
S3C44B0X datasheets
 

Specifications of S3C44B0X

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PRODUCT OVERVIEW
FEATURES
Architecture
Integrated system for hand-held devices and
general embedded applications.
16/32-Bit RISC architecture and powerful
instruction set with ARM920T CPU core.
Enhanced ARM architecture MMU to support
WinCE, EPOC 32 and Linux.
Instruction cache, data cache, write buffer and
Physical address TAG RAM to reduce the effect
of main memory bandwidth and latency on
performance.
ARM920T CPU core supports the ARM debug
architecture and has a Tracking ICE mode.
Internal AMBA(Advanced Microcontroller Bus
Architecture) (AMBA2.0, AHB/APB)
System Manager
Little/Big Endian support.
Address space: 32M bytes for each bank
(Total 256Mbyte)
Supports programmable 8/16/32-bit data bus
width for each bank.
Fixed bank start address and programmable bank
size for 7 banks.
Programmable bank start address and bank size
for one bank.
8 memory banks.
— 6 memory banks for ROM, SRAM etc.
— 2 memory banks for ROM/SRAM/DRAM(EDO
or Synchronous DRAM)
Fully Programmable access cycles for all
memory banks.
Supports external wait signal to expend the bus
cycle.
Supports self-refresh mode in DRAM/SDRAM for
power-down.
Supports asymmetric/symmetric address of
DRAM.
1-2
S3C2400 RISC MICROPROCESSOR
Cache Memory
64 way set-associative cache with I-Cache(16KB)
and D-Cache(16KB).
8-words per line with one valid bit and two dirty
bits per line
Pseudo random or round robin replacement
algorithm.
Write through or write back cache operation to
update the main memory.
The write buffer can hold 16 words of data and four
address.
Clock & Power Manager
Low power
The on-chip MPLL and UPLL
UPLL makes the clock for operating USB
Host/Device.
MPLL makes the clock for operating MCU at
maximum 150Mhz @ 1.8V.
Clock can be fed selectively to each function
block by software.
Power mode: Normal, Slow, Idle, Stop mode and
SL_IDLE mode.
Normal mode: Normal operating mode.
Slow mode: Low frequency clock without PLL.
Idle mode: Stop the clock for only CPU.
Stop mode: All clocks are stopped.
SL_IDLE mode: All clocks except LCD are
stopped.
Wake up by EINT[7:0] or RTC alarm interrupt from
Stop mode.
Interrupt Controller
32 Interrupt sources
(Watch dog timer, 5Timer, 6UART, 8External
interrupts, 4 DMA, 2 RTC, 1 ADC, 1 IIC, 1 SPI, 1
MMC, 2 USB)
Level/Edge mode on external interrupt source.
Programmable polarity of edge and level.
Supports FIQ (Fast Interrupt request) for very
urgent interrupt request.