S3C44B0X Samsung, S3C44B0X Datasheet - Page 207

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S3C44B0X

Manufacturer Part Number
S3C44B0X
Description
BGA
Manufacturer
Samsung
Datasheets

Specifications of S3C44B0X

Date_code
02+
CLOCK & POWER MANAGEMENT
CLOCK CONTROL REGISTER (CLKCON)
Register
Address
CLKCON
0x1480000C
CLKCON
Bit
SPI
[15]
IIS
[14]
IIC
[13]
ADC
[12]
RTC
[11]
GPIO
[10]
UART1
[9]
UART0
[8]
MMC
[7]
PWMTIMER
[6]
USB device
[5]
USB host
[4]
LCDC
[3]
IDLE BIT
[2]
SL_IDLE
[1]
STOP BIT
[0]
6-24
R/W
Description
R/W
Clock generator control Register
Description
Controls PCLK into SPI block
0 = Disable,
1 = Enable
Controls PCLK into IIS block
0 = Disable,
1 = Enable
Controls PCLK into IIC block
0 = Disable,
1 = Enable
Controls PCLK into ADC block
0 = Disable,
1 = Enable
Controls PCLK into RTC control block.
Even if this bit is cleared to 0, RTC timer is alive.
0 = Disable,
1 = Enable
Controls PCLK into GPIO block
0 = Disable,
1 = Enable
Controls PCLK into UART1 block
0 = Disable,
1 = Enable
Controls PCLK into UART0 block
0 = Disable,
1 = Enable
Controls PCLK into MMC interface block
0 = Disable,
1 = Enable
Controls PCLK into PWMTIMER block
0 = Disable,
1 = Enable
Controls PCLK into USB device block
0 = Disable,
1 = Enable
Controls HCLK into USB host block
0 = Disable,
1 = Enable
Controls HCLK into LCDC block
0 = Disable,
1 = Enable
Enters IDLE mode. This bit isn't be cleared automatically.
0 = Disable,
1 = Transition to IDLE(SL_IDLE) mode
SL_IDLE mode option. This bit isn't be cleared automatically.
0 = Disable,
1 = SL_IDLE mode.
To enter SL_IDLE mode, CLKCON register has to be 0xe.
Enters STOP mode. This bit isn't be cleared automatically.
0 = Disable
1 = Transition to STOP mode
S3C2400 RISC MICROPROCESSOR
Reset Value
0xfff8
Initial State
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0

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