S3C44B0X Samsung, S3C44B0X Datasheet - Page 208
Manufacturer Part Number
Specifications of S3C44B0X
S3C2400 RISC MICROPROCESSOR
CLOCK SLOW CONTROL REGISTER (CLKSLOW)
CLOCK DIVIDER CONTROL REGISTER (CLKDIVN)
Slow clock control register
0 = UCLK ON (UPLL is also turned on and the UPLL lock time
is inserted automatically.)
1 = UCLK OFF(UPLL is also turned off)
0 = PLL is turned on.
After PLL stabilization time (minimum 150us), SLOW_BIT
can be cleared to 0.
1 = PLL is turned off.
PLL is turned off only when SLOW_BIT is 1.
0 = FCLK = Mpll (MPLL output)
1 = SLOW mode
FCLK = input clock / (2 x SLOW_VAL) (SLOW_VAL > 0)
FCLK = input clock
input clock = XTIpll or EXTCLK
The divider value for the slow clock when SLOW_BIT is on.
Clock divider control register
0 = HCLK has the clock same as the FCLK
1 = HCLK has the clock same as the FCLK/2
0 = PCLK has the clock same as the HCLK
1 = PCLK has the clock same as the HCLK/2
CLOCK & POWER MANAGEMENT
(SLOW_VAL = 0)