S3C44B0X Samsung, S3C44B0X Datasheet - Page 208

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S3C44B0X

Manufacturer Part Number
S3C44B0X
Description
BGA
Manufacturer
Samsung
Datasheets

Specifications of S3C44B0X

Date_code
02+
S3C2400 RISC MICROPROCESSOR
CLOCK SLOW CONTROL REGISTER (CLKSLOW)
Register
Address
CLKSLOW
0x14800010
CLKSLOW
Bit
UCLK_ON
[7]
Reserved
[6]
MPLL_OFF
[5]
SLOW_BIT
[4]
SLOW_VAL
[2:0]
CLOCK DIVIDER CONTROL REGISTER (CLKDIVN)
Register
Address
CLKDIVN
0x14800014
CLKDIVN
Bit
HDIVN
[1]
PDIVN
[0]
R/W
Description
R/W
Slow clock control register
Description
0 = UCLK ON (UPLL is also turned on and the UPLL lock time
is inserted automatically.)
1 = UCLK OFF(UPLL is also turned off)
Reserved
0 = PLL is turned on.
After PLL stabilization time (minimum 150us), SLOW_BIT
can be cleared to 0.
1 = PLL is turned off.
PLL is turned off only when SLOW_BIT is 1.
0 = FCLK = Mpll (MPLL output)
1 = SLOW mode
FCLK = input clock / (2 x SLOW_VAL) (SLOW_VAL > 0)
FCLK = input clock
input clock = XTIpll or EXTCLK
The divider value for the slow clock when SLOW_BIT is on.
R/W
Description
R/W
Clock divider control register
Description
0 = HCLK has the clock same as the FCLK
1 = HCLK has the clock same as the FCLK/2
0 = PCLK has the clock same as the HCLK
1 = PCLK has the clock same as the HCLK/2
CLOCK & POWER MANAGEMENT
Reset Value
0x00000004
Initial State
0
0
0
(SLOW_VAL = 0)
0x4
Reset Value
0x00000000
Initial State
0
0
6-25

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