S3C44B0X

Manufacturer Part NumberS3C44B0X
DescriptionBGA
ManufacturerSamsung
S3C44B0X datasheets
 


Specifications of S3C44B0X

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DMA
DMA REQUEST SOURCES
Each channel of DMA controller can select one of DMA request source among four DMA sources if H/W DMA
request mode is selected by DCON register. (Note that if S/W request mode is selected, this DMA request sources
have no meaning at all.) The four DMA sources for each channel are as follows.
Table 8-1. DMA request sources for each channel
Source0
Ch-0
nXDREQ0
Ch-1
nXDREQ1
Ch-2
I2SSDO
Ch-3
USB device
Here, nXDREQ0 and nXDREQ1 represent two external sources(External Devices), and I2SSDO and I2SSDI represent
IIS transmitting and receiving, respectively.
DMA OPERATION
The details of DMA operation can be explained using three-state FSM(finite state machine) as follows:
State-1.
As an initial state, it waits for the DMA request. If it comes, go to state-2. At this state, DMA ACK
and INT REQ are 0.
State-2.
In this state, DMA ACK becomes 1 and the counter(CURR_TC) is loaded from DCON[19:0]
register. Note that DMA ACK becomes 1 and remains 1 until it is cleared later.
State-3.
In this state, sub-FSM handling the atomic operation of DMA is initiated. The sub-FSM reads the
data from the source address and then writes it to destination address. In this operation, data size
and transfer size (single or burst) are considered. This operation is repeated until the
counter(CURR_TC) becomes 0 in the whole service mode, while performed only once in a single
service mode. The main FSM (this FSM) counts down the CURR_TC when the sub-FSM finishes
each of atomic operation. In addition, this main FSM asserts the INT REQ signal when
CURR_TC becomes 0 and the interrupt setting of DCON[28] register is set to 1. In addition, it
clears DMA ACK if one of the following conditions are met.
1) CURR_TC becomes 0 in the whole service mode
2) atomic operation finishes in the single service mode.
Note that in the single service mode, these three states of main FSM are performed and then stops, and waits for
another DMA REQ. And if DMA REQ comes in all three states are repeated. Therefore, DMA ACK is asserted and
then de-asserted for each atomic transfer. In contrast, in the whole service mode, main FSM waits at state-3 until
CURR_TC becomes 0. Therefore, DMA ACK is asserted during all the transfers and then de-asserted when TC
reaches 0.
However, INT REQ is asserted only if CURR_TC becomes 0 regardless of the service mode (single service mode or
whole service mode).
8-2
S3C2400 RISC MICROPROCESSOR
Source1
Source2
UART0
MMC
UART1
I2SSDI
I2SSDI
MMC
MMC
SPI
Source3
Timer
SPI
Timer
Timer