S3C44B0X

Manufacturer Part NumberS3C44B0X
DescriptionBGA
ManufacturerSamsung
S3C44B0X datasheets
 


Specifications of S3C44B0X

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S3C2400 RISC MICROPROCESSOR
DMA CONTROL REGISTER (DCON)
Register
Address
DCON0
0x14600008
DCON1
0x14600028
DCON2
0x14600048
DCON3
0x14600068
DCONn
Bit
DMD_HS
[30]
Select one between demand mode and handshake mode.
0 = demand mode is selected
1 = handshake mode is selected.
In both modes, DMA controller starts its transfer and asserts DACK
for a given asserted DREQ. The difference between two modes is
whether it waits for the de-asserted DACK or not. In handshake mode,
DMA controller waits for the de-asserted DREQ before starting a new
transfer. If it sees the de-asserted DREQ, it de-asserts DACK and
waits for another asserted DREQ. In contrast, in the demand mode,
DMA controller does not wait until the DREQ is de-asserted. It just
de-asserts DACK and then starts another transfer if DREQ is
asserted. We recommend using handshake mode for external DMA
request sources to prevent unintended starts of new transfers.
SYNC
[29]
Select DREQ/DACK synchronization.
0 = DREQ and DACK are synchronized to PCLK (APB clock).
1 = DREQ and DACK are synchronized to HCLK (AHB clock).
Therefore, devices attached to AHB system bus, this bit has to be set
to 1, while those attached to APB system, it should be set to 0. For
the devices attached to external system, user should select this bit
depending on whether the external system is synchronized with AHB
system or APB system.
INT
[28]
Enable/Disable the interrupt setting for CURR_TC(terminal count)
0 = CURR_TC interrupt is disabled. user has to look the transfer count
in the status register. (i.e., polling)
1 = interrupt request is generated when all the transfer is done (i.e.,
CURR_TC becomes 0).
TSZ
[27]
Select the transfer size of an atomic transfer (i.e., transfer performed
at each time DMA owns the bus before releasing the bus).
0 = a unit transfer is performed.
1 = a burst transfer of length four is performed.
R/W
Description
R/W
DMA 0 Control Register
R/W
DMA 1 Control Register
R/W
DMA 2 Control Register
R/W
DMA 3 Control Register
Description
DMA
Reset Value
0x00000000
0x00000000
0x00000000
0x00000000
Initial State
0
0
0
0
8-9