S3C44B0X

Manufacturer Part NumberS3C44B0X
DescriptionBGA
ManufacturerSamsung
S3C44B0X datasheets
 

Specifications of S3C44B0X

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S3C2400 RISC MICROPROCESSOR
DCONn
Bit
SERVMODE
[26]
Select the service mode between single service mode and whole
service mode.
0: single service mode is selected in which after each atomic transfer
(single or burst of length four) DMA stops and waits for another DMA
request.
1: whole service mode is selected in which one request gets atomic
transfers to be repeated until the transfer count reaches to 0. In this
mode, additional request is not required. Here, note that even in the
whole service mode, DMA releases the bus after each atomic transfer
and then tries to re-get the bus to prevent starving of other bus
masters.
HWSRCSEL
[25:24]
Select DMA request source for each DMA.
DCON0: 00: nXDREQ0
DCON1: 00: nXDREQ1
DCON2: 00:I2SSDO
DCON3: 00:USB device
This bits control the 4-1 MUX to select the DMA request source of
each DMA. These bits have meanings if and only if H/W request mode
is selected by DCONn[23].
SWHW_SEL
[23]
Select the DMA source between software (S/W request mode) and
hardware (H/W request mode).
0: S/W request mode is selected and DMA is triggered by setting
SW_TRIG bit of DMASKTRIG control register.
1: DMA source selected by bit[25:24] is used to trigger the DMA
operation.
RELOAD
[22]
Set the reload on/off option.
0 = auto reload is performed when a current value of transfer count
becomes 0 (i.e., all the required transfers are performed).
1 = DMA channel(DMA REQ) is turned off when a current value of
transfer count becomes 0. The channel on/off bit(DMASKTRIGn[1]) is
set to 0(DREQ off) to prevent unintended further start of new DMA
operation
DSZ
[21:20]
Data size to be transferred.
00 = Byte
10 = Word
TC
[19:0]
Initial transfer count (or transfer beat).
Note that the actual number of bytes that are transferred is computed
by the following equation: DSZ x TSZ x TC, where DSZ, TSZ, and TC
represent data size (DCONn[21:20]), transfer size (DCONn[27]), and
initial transfer count, respectively.
This value will be loaded into CURR_SRC only if the CURR_SRC is 0
and the DMA ACK is 1.
Description
01:UART0
10:MMC
01:UART1
10:I2SSDI
01:I2SSDI
10:MMC
01:MMC
10:SPI
01 = Half word
11 = reserved
DMA
Initial State
0
00
11:Timer
11:SPI
11:Timer
11:Timer
0
0
00
00000
8-10