S3C44B0X

Manufacturer Part NumberS3C44B0X
DescriptionBGA
ManufacturerSamsung
S3C44B0X datasheets
 


Specifications of S3C44B0X

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S3C2400 RISC MICROPROCESSOR
DMA MASK TRIGGER REGISTER (DMASKTRIG)
Register
Address
DMASKTRIG0
0x14600018
DMASKTRIG1
0x14600038
DMASKTRIG2
0x14600058
DMASKTRIG3
0x14600078
DMASKTRIGn
Bit
STOP
[2]
Stop the DMA operation.
1 = DMA stops as soon as the current atomic transfer ends. If there
is no current running atomic transfer, DMA stops immediately. The
CURR_TC, CURR_SRC, CURR_DST will be 0.
NOTE: Due to possible current atomic transfer, “stop” may take several
cycles. The finish of “stopping” operation (i.e., actual stop time) can be
detected by waiting until the channel on/off bit(DMASKTRIGn[1]) is set to
off. This stop is “actual stop”.
ON_OFF
[1]
DMA channel on/off bit.
0 = DMA channel is turned off. (DMA request to this channel is
ignored.)
1 = DMA channel is turned on and the DMA request is handled. This
bit is automatically set to off if we set the DCONn[22] bit to “no auto
reload” and/or STOP bit of DMASKTRIGn to “stop”.
Note that when DCON[22] bit is "no auto reload", this bit becomes 0
when CURR_TC reaches 0. If the STOP bit is 1, this bit becomes 0
as soon as the current atomic transfer finishes.
NOTE: This bit should not be changed manually during DMA operations
(i.e., this has to be changed only by using DCON[22] or STOP bit.)
SW_TRIG
[0]
Trigger the DMA channel in S/W request mode.
1 = it requests a DMA operation to this controller.
However, note that for this trigger to have effects S/W request mode
has to be selected (DCONn[23]) and channel ON_OFF bit has to be
set to 1 (channel on). When DMA operation starts, this bit is cleared
automatically.
NOTE:
You can freely change the values of DISRC register, DIDST registers, and TC field of DCON register. Those
changes take effect only after the FINISH of current transfer (i.e., when CURR_TC becomes 0). On the other hand,
any change made to other registers and/or fields takes immediate effect. Therefore, be careful in changing those
registers and fields.
R/W
Description
R/W
DMA 0 Mask Trigger Register
R/W
DMA 1 Mask Trigger Register
R/W
DMA 2 Mask Trigger Register
R/W
DMA 3 Mask Trigger Register
Description
DMA
Reset Value
000
000
000
000
Initial State
0
0
0
8-13