S3C44B0X Samsung, S3C44B0X Datasheet - Page 268
Manufacturer Part Number
Specifications of S3C44B0X
S3C2400 RISC MICROPROCESSOR
The following sections describe the UART operations that include data transmission, data reception, interrupt
generation, baud-rate generation, loopback mode, infra-red mode, and auto flow control.
The data frame for transmission is programmable. It consists of a start bit, 5 to 8 data bits, an optional parity bit and
1 to 2 stop bits, which can be specified by the line control register (ULCONn). The transmitter can also produce the
break condition. The break condition forces the serial output to logic 0 state for one frame transmission time. This
block transmits break signal after the present transmission word transmits perfectly. After the break signal
transmission, it continously transmits data into the Tx FIFO (Tx holding register in the case of Non-FIFO mode).
Like the transmission, the data frame for reception is also programmable. It consists of a start bit, 5 to 8 data bits,
an optional parity bit and 1 to 2 stop bits in the line control register (ULCONn). The receiver can detect overrun error,
parity error, frame error and break condition, each of which can set an error flag.
— The overrun error indicates that new data has overwritten the old data before the old data has been read.
— The parity error indicates that the receiver has detected an unexpected parity condition.
— The frame error indicates that the received data does not have a valid stop bit.
— The break condition indicates that the RxDn input is held in the logic 0 state for a duration longer than one
frame transmission time.
Receive time-out condition occurs when it does not receive data during the 3 word time(This interval follows the
setting of Word Length bit) and the Rx FIFO is not empty in the FIFO mode.
Auto Flow Control(AFC)
S3C2400's UART supports auto flow control with nRTS and nCTS signals, in case it would have to connect UART to
UART. If users connect UART to a Modem, disable auto flow control bit in UMCONn register and control the signal of
nRTS by software.
In AFC, nRTS is controlled by condition of the receiver and operation of transmitter is controlled by the nCTS signal.
The UART's transmitter transfers the data in FIFO only when nCTS signal active(In AFC, nCTS means that the other
UART's FIFO is ready to receive data). Before the UART receives data, nRTS has to be activated when its receive
FIFO has a spare more than 2-byte and has to be inactivated when its receive FIFO has a spare under 1-byte(In
AFC, nRTS means that its own receive FIFO is ready to receive data).
Transmission case in
Reception case in
Figure 11-2. UART AFC interface