S3C44B0X Samsung, S3C44B0X Datasheet - Page 271

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S3C44B0X

Manufacturer Part Number
S3C44B0X
Description
BGA
Manufacturer
Samsung
Datasheets

Specifications of S3C44B0X

Date_code
02+
UART
UART Error Status FIFO
UART has the status FIFO besides the Rx FIFO register. The status FIFO indicates which data, among FIFO
registers, is received with an error. The error interrupt will be issued only when the data, which has an error, is ready
to read out. To clear the status FIFO, the URXHn with an error and UERSTATn must be read out.
For example,
It is assumed that the UART FIFO receives A, B, C, D, E characters sequentially and the frame error occurrs while
receiving 'B', and the parity error occurs while receiving 'D'.
Although the actual UART error occurred, the error interrupt will not be generated because the character, which was
received with an error, has not been read yet. The error interrupt will occur when the character is read out.
Time
Sequence flow
#0
When no character is read out
#1
After A is read out
#2
After B is read out
#3
After C is read out
#4
After D is read out
#5
After E is read out
RX-FIFO
Figure 11-3. A Case showing UART Receiving 5 Characters with 2 Errors
11-6
Error interrupt
The frame error(in B) interrupt occurs
The parity error(in D) interrupt occurs
STATUS-FIFO
break error
parity error
-
-
-
-
-
-
-
-
-
-
-
'E'
'D'
'C'
'B'
'A'
URXHn
Error Status Generator Unit
S3C2400 RISC MICROPROCESSOR
Note
The 'B' has to be read out
The 'D' has to be read out
frame error

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