S3C44B0X

Manufacturer Part NumberS3C44B0X
DescriptionBGA
ManufacturerSamsung
S3C44B0X datasheets
 

Specifications of S3C44B0X

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S3C2400 RISC MICROPROCESSOR
EPn_IN_CSR
Bit
FIFO_FLUSH
[2]
Reserved
[1]
IN_PKT_RDY
[0]
MCU
USB
W/
CLEAR
The MCU sets this bit if it intends to flush
CLEAR
the packet in Input-related FIFO. This bit
is cleared by the USB when the FIFO is
flushed. The MCU is interrupted when this
happens. If a token is in process, the USB
waits until the transmission is complete
before FIFO flushing.
If two packets are loaded into the FIFO,
only first packet (The packet is intended
to be sent to the host) is flushed, and the
corresponding IN_PKT_RDY bit is cleared
SET/
CLEAR
The MCU sets this bit after writing a
R
packet data into the FIFO. The USB
clears this bit once the packet has been
successfully sent to the host.
An interrupt is generated when the USB
clears this bit so as the MCU to load the
next packet.
While this bit is set by MCU after writing a
packet data into the FIFO, the MCU will
not be able to write a new packet data to
the FIFO without clearing by USB. If the
SEND_STALL bit is set by the MCU, this
bit also cannot be set.
USB DEVICE
Description
Initial State
0
0
0
13-11