S3C44B0X Samsung, S3C44B0X Datasheet - Page 298

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S3C44B0X

Manufacturer Part Number
S3C44B0X
Description
BGA
Manufacturer
Samsung
Datasheets

Specifications of S3C44B0X

Date_code
02+
S3C2400X01 RISC MICROPROCESSOR
END POINT OUT CONTROL STATUS REGISTER
Register
Address
EP3_OUT_CSR
0x152001A0
EP4_OUT_CSR
0x152001B0
EPn_OUT_CSR
Bit
Reserved
[31:8]
AUTO_CLR
[7]
DMA_OPR_INT
[6]
_MASK
CLR_DATA
[5]
_TOGGLE
SENT_STALL
[4]
SEND_STALL
[3]
FIFO_FLUSH
[2]
Reserved
[1]
OUT_PKT_RDY
[0]
R/W
R/W
End Point3 out control status register
R/W
End Point4 out control status register
MCU
USB
R/W
R
If MCU set, whenever the MCU reads
data from the OUT FIFO,
OUT_PKT_RDY will automatically be
cleared by the logic, without any
intervention from MCU.
R/W
R
This bit determines whether the
interrupt should be issued, or not, when
the EP3 OUT_PKT_RDY condition
happens. This is only useful for DMA
mode
0 = Interrupt Enable
1 = Interrupt Masking
R/W
CLEAR
When the MCU writes a 1 to this bit,
the data toggle sequence bit is reset to
DATA0.
CLEAR
SET
The USB sets this bit when an OUT
/R
token is ended with a STALL
handshake. The USB issues a stall
handshake to the host if it sends more
than MAXP data for the OUT TOKEN.
R/W
R
0 = The MCU clears this bit to end the
STALL condition handshake,
IN PKT RDY is cleared.
1 = The MCU issues a STALL
handshake to the USB.
The MCU clears this bit to end the
STALL condition handshake, IN PKT
RDY is cleared.
R/W
CLEAR
The MCU write a 1 to flush the FIFO.
This bit can be set only when
OUT_PKT_RDY (D0) is set. The
packet due to be unloaded by the MCU
will be flushed.
R/
SET
The USB sets this bit after it has
CLEAR
loaded a packet of data into the FIFO.
Once the MCU reads the packet from
FIFO, this bit should be cleared by
MCU. (Write a "0")
Description
Reset Value
0x00000000
0x00000000
Description
Initial State
USB DEVICE
0
0
0
0
0
0
0
0
0
13-13

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