S3C44B0X

Manufacturer Part NumberS3C44B0X
DescriptionBGA
ManufacturerSamsung
S3C44B0X datasheets
 


Specifications of S3C44B0X

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INTERRUPT CONTROLLER
S3C2400 RISC MICROPROCESSOR
INTERRUPT CONTROLLER OPERATION
F-bit and I-bit of PSR (program status register)
If the F-bit of PSR (program status register in ARM920T CPU) is set to 1, the CPU does not accept the FIQ (fast
interrupt request) from the interrupt controller. If I-bit of PSR (program status register in ARM920T CPU) is set to 1,
the CPU does not accept the IRQ (interrupt request) from the interrupt controller. So, to enable the interrupt
reception, the F-bit or I-bit of PSR has to be cleared to 0 and also the corresponding bit of INTMSK has to be set to
0.
Interrupt Mode
ARM920T has 2 types of interrupt mode, FIQ or IRQ. All the interrupt sources determine the mode of interrupt to be
used at interrupt request.
Interrupt Pending Register
S3C2400X01 has two interrupt pending resisters. The one is source pending register(SRCPND), the other is interrupt
pending register(INTPND). These pending registers indicate whether or not an interrupt request is pending. When the
interrupt sources request interrupt service the corresponding bits of SRCPND register are set to 1, at the same time
the only one bit of INTPND register is set to 1 automatically after arbitration process. If interrupts are masked, the
corresponding bits of SRCPND register are set to 1, but the bit of INTPND register is not changed. When a pending
bit of INTPND register is set, the interrupt service routine starts whenever the I-flag or F-flag is cleared to 0. The
SRCPND and INTPND registers can be read and written, so the service routine must clear the pending condition by
writing a 1 to the corresponding bit in SRCPND register first and then clear the pending condition in INTPND registers
same method.
Interrupt Mask Register
Indicates that an interrupt has been disabled if the corresponding mask bit is 1. If an interrupt mask bit of INTMSK is
0, the interrupt will be serviced normally. If the corresponding mask bit is 1 and the interrupt is generated, the source
pending bit will be set.
14-2