S3C44B0X

Manufacturer Part NumberS3C44B0X
DescriptionBGA
ManufacturerSamsung
S3C44B0X datasheets
 

Specifications of S3C44B0X

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S3C2400 RISC MICROPROCESSOR
LCD CONTROLLER
LCD Self Refresh Mode
The LCD controller within S3C2400X01 can support the self refresh mode to reduce power comsumption. The self
refresh mode can only be applied to only the LCD which has the special LCD driver, for example, LCD panel of
SED1580D from Seiko Epson Corporation. The SED1580D has the built-in monochrome display memory, which can
display the previous stored image in the built-in monochrome display memory without image data fetch when the self
refresh mode has been invoked. But SED1580D has the built-in display memory for monochrome only. So, the user
has to set one more frame as a monochrome mode before the entering to self refresh mode. The kind of self refresh
mode can be made by writing the control bit of SELFREF in the LCDCON5 register.
If the SELFREF bit is set to 1, the LCD controller enters into the self refresh mode from the next line. When the LCD
controller enters into the self refresh mode, the signal of VCLK and VD should be fixed as Low and last data value,
but the signal of VM, VFRAME, and VLINE will be generated continuously. To exit the self refresh mode, the user
should disable SELFREF bit in LCDCON 5 register.
SL_IDLE Mode (LCD dedicated Idle Mode)
The SL_IDLE mode in the power management scheme should be used to enter into the LCD driver's self refresh
mode. In SL_IDLE mode, all function blocks except the LCD controller within S3C2400X01should be stopped to
reduce the power comsumption, because the power management block inserts divide_by_n input clock only to the
LCD controller. For more information, please refer to the chapter, clock & power management and our example
source code.
Timing Requirements
Image data should be transferred from the memory to the LCD driver using the VD[7:0] signal. VCLK signal is used
to clock the data into the LCD driver's shift register. After each horizontal line of data has been shifted into the LCD
driver's shift register, the VLINE signal is asserted to display the line on the panel.
The VM signal provides an AC signal for the display. It is used by the LCD to alternate the polarity of the row and
column voltages, used to turn the pixels on and off, because the LCD plasma tends to deteriorate whenever
subjected to a DC voltage. It can be configured to toggle on every frame or to toggle every programmable number of
VLINE signals.
Figure 15-5 shows the timing requirements for the LCD driver interface.
15-11