S3C44B0X

Manufacturer Part NumberS3C44B0X
DescriptionBGA
ManufacturerSamsung
S3C44B0X datasheets
 

Specifications of S3C44B0X

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S3C2400 RISC MICROPROCESSOR
IIC-BUS INTERFACE
READ-WRITE OPERATION
In the transmitter mode, after the data is transferred, the IIC-bus interface will wait until IICDS(IIC-bus Data Shift
Register) is written by a new data. Until the new data is written, the SCL line will be held low. After the new data is
written to IICDS register, the SCL line will be released. The S3C2400X01 should hold the interrupt to identify the
completion of current data transfer. After the CPU receives the interrupt request, it should write a new data into
IICDS, again.
In the receive mode, after a data is received, the IIC-bus interface will wait until IICDS register is read. Until the new
data is read out, the SCL line will be held low. After the new data is read out from IICDS register, the SCL line will be
released. The S3C2400X01 should hold the interrupt to identify the completion of the new data reception. After the
CPU receives the interrupt request, it should read the data from IICDS.
BUS ARBITRATION PROCEDURES
Arbitration takes place on the SDA line to prevent the contention on the bus between two masters. If a master with a
SDA High level detects another master with a SDA active Low level, it will not initiate a data transfer because the
current level on the bus does not correspond to its own. The arbitration procedure will be extended until the SDA line
turns High.
However when the masters simultaneously lower the SDA line, each master should evaluate whether or not the
mastership is allocated to itself. For the purpose of evaluation, each master should detect the address bits. While
each master generates the slaver address, it should also detect the address bit on the SDA line because the
lowering of SDA line is stronger than maintaining High on the line. For example, one master generates a Low as first
address bit, while the other master is maintaining High. In this case, both masters will detect Low on the bus
because Low is stronger than High even if first master is trying to maintain High on the line. When this happens,
Low(as the first bit of address) -generating master will get the mastership and High(as the first bit of address) -
generating master should withdraw the mastership. If both masters generate Low as the first bit of address, there
should be an arbitration for second address bit, again. This arbitration will continue to the end of last address bit.
ABORT CONDITIONS
If a slave receiver can not acknowledge the confirmation of the slave address, it should hold the level of the SDA line
High. In this case, the master should generate a Stop condition and to abort the transfer.
If a master receiver is involved in the aborted transfer, it should signal the end of the slave transmit operation by
canceling the generation of an ACK after the last data byte received from the slave. The slave transmitter should then
release the SDA to allow a master to generate a Stop condition.
CONFIGURING THE IIC-BUS
To control the frequency of the serial clock (SCL), the 4-bit prescaler value can be programmed in the IICCON
register. The IIC-bus interface address is stored in the IIC-bus address register, IICADD. (By default, the IIC-bus
interface address is an unknown value.)
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