S3C44B0X Samsung, S3C44B0X Datasheet - Page 416

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S3C44B0X

Manufacturer Part Number
S3C44B0X
Description
BGA
Manufacturer
Samsung
Datasheets

Specifications of S3C44B0X

Date_code
02+
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IIS-BUS INTERFACE
BLOCK DIAGRAM
FUNCTIONAL DESCRIPTIONS
Bus interface, register bank, and state machine (BRFC) - Bus interface logic and FIFO access are controlled by the
state machine.
5-bit dual prescaler (IPSR) - One prescaler is used as the master clock generator of the IIS bus interface and the
other is used as the external CODEC clock generator.
16-byte FIFOs (TXFIFO, RXFIFO) - In transmit data transfer, data are written to TXFIFO, and, in the receive data
transfer, data are read from RXFIFO.
Master IISCLK generaor (SCLKG) - In master mode, serial bit clock is generated from the master clock.
Channel generator and state machine (CHNC) - IISCLK and IISLRCK are generated and controlled by the channel
state machine.
16-bit shift register (SFTR) - Parallel data is shifted to serial data output in the transmit mode, and serial data input
is shifted to parallel data in the receive mode.
21-2
ADDR
DATA
CNTL
PCLK
IPSR_A
IPSR_B
BRFC
Figure 21-1. IIS-Bus Block Diagram
RxFIFO
TxFIFO
SCLKG
CHNC
S3C2400 RISC MICROPROCESSOR
SFTR
SD
SCLK
LRCK
CDCLK

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