Bus interface, register bank, and state machine (BRFC) - Bus interface logic and FIFO access are controlled by the
5-bit dual prescaler (IPSR) - One prescaler is used as the master clock generator of the IIS bus interface and the
other is used as the external CODEC clock generator.
16-byte FIFOs (TXFIFO, RXFIFO) - In transmit data transfer, data are written to TXFIFO, and, in the receive data
transfer, data are read from RXFIFO.
Master IISCLK generaor (SCLKG) - In master mode, serial bit clock is generated from the master clock.
Channel generator and state machine (CHNC) - IISCLK and IISLRCK are generated and controlled by the channel
16-bit shift register (SFTR) - Parallel data is shifted to serial data output in the transmit mode, and serial data input
is shifted to parallel data in the receive mode.
Figure 21-1. IIS-Bus Block Diagram
S3C2400 RISC MICROPROCESSOR