S3C44B0X Samsung, S3C44B0X Datasheet - Page 422

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S3C44B0X

Manufacturer Part Number
S3C44B0X
Description
BGA
Manufacturer
Samsung
Datasheets

Specifications of S3C44B0X

Date_code
02+
IIS-BUS INTERFACE
IIS PRESCALER REGISTER (IISPSR)
Register
Address
IISPSR
0x15508008(Li/HW, Li/W, Bi/W)
0x1550800A(Bi/HW)
IISPSR
Bit
Prescaler
[9:5]
Data value: 0 – 31
control A
NOTE: Prescaler A makes the master clock that is used the
Prescaler
[4:0]
Data value: 0 – 31
control B
NOTE: Prescaler B makes the master clock that is used the
NOTES:
1.
The IISPSR register can be accessed by byte, halfword and word unit using STRB/STRH/STR and LDRB/LDRH/LDR
instructions or char/short int/int type pointer in Little/Big endian mode.
2.
(Li/B/HW/W): Access by byte/halfword/word unit when the endian mode is Little.
(Bi/B/HW/W): Access by byte/halfword/word unit when the endian mode is Big.
IIS FIFO CONTROL REGISTER (IISFCON)
Register
Address
IISFCON
0x1550800C(Li/HW, Li/W, Bi/W)
0x1550800E(Bi/HW)
IISFCON
Transmit FIFO access mode
select
Receive FIFO access mode
select
Transmit FFO enable
Receive FIFO enable
Transmit FIFO data count
(read only)
Receive FIFO data count
(read only)
NOTES:
1.
The IISFCON register can be accessed by halfword and word unit using STRH/STR and LDRH/LDR instructions or
short
int/int type pointer in Little/Big endian mode.
2.
(Li/HW/W): Access by halfword/word unit when the endian mode is Little.
(Bi/HW/W): Access by halfword/word unit when the endian mode is Big.
21-8
R/W
R/W
Description
internal block and division factor is N+1.
external block and division factor is N+1.
R/W
R/W
Bit
Description
[11]
0 = Normal access mode
1 = DMA access mode
[10]
0 = Normal access mode
1 = DMA access mode
[9]
0 = FIFO disable
1 = FIFO enable
[8]
0 = FIFO disable
1 = FIFO enable
[7:4]
Data count value = 0 ~ 8
[3:0]
Data count value = 0 ~ 8
S3C2400 RISC MICROPROCESSOR
Description
Reset Value
IIS prescaler register
Initial State
Description
Reset Value
IIS FIFO interface register
Initial State
0x0
0
000
0x0
0
0
0
0
000
000

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