UPD720101GJUENA NEC, UPD720101GJUENA Datasheet

UPD720101GJUENA

Manufacturer Part Number

UPD720101GJUENA

Description

QFP

Manufacturer

NEC

Datasheet

1.UPD720101F1EA8A.pdf (36 pages)

Specifications of UPD720101GJUENA

Date_code

09+

Current page: 1 of 36
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Document No.

Date Published March 2005 NS CP (N)

Printed in Japan

Interface Specification for full-/low-speed signaling and Intel's Enhanced Host Controller Interface Specification for

high-speed signaling and works up to 480 Mbps. The

interface and USB 2.0 transceivers into a single chip.

FEATURES

• Compliant with Universal Serial Bus Specification Revision 2.0 (Data rate 1.5/12/480 Mbps)

• Compliant with Open Host Controller Interface Specification for USB Rev 1.0a

• Compliant with Enhanced Host Controller Interface Specification for USB Rev 1.0

• PCI multi-function device consists of two OHCI host controller cores for full-/low-speed signaling and one EHCI

• Root hub with 5 (max.) downstream facing ports which are shared by OHCI and EHCI host controller cores.

• All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps)

• Configurable number of downstream facing ports (2 to 5)

• 32-bit 33 MHz host interface compliant to PCI Specification release 2.2

• Supports PCI Mobile Design Guide Revision 1.1

• Supports PCI-Bus Power Management Interface Specification release 1.1

• PCI bus bus-master access

• System clock is generated by 30 MHz X’tal or 48 MHz clock input.

• Operational registers direct-mapped to PCI memory space

• Legacy support for all downstream facing ports. Legacy support features allow easy migration for motherboard

• 3.3 V power supply, PCI signal pins have 5 V tolerant circuit.

ORDERING INFORMATION

Detailed function descriptions are provided in the following user’s manual. Be sure to read the manual before designing.

The

implementation.

host controller core for high-speed signaling.

transaction.

− System clock frequency should be set from system software (BIOS) or EEPROM. More detail, see

S16265EJ5V0DS00 (5th edition)

PD720101GJ-UEN

PD720101GJ-UEN-A

PD720101F1-EA8

PD720101F1-EA8-A

User’s Manual.

Part Number

PD720101 complies with the Universal Serial Bus Specification Revision 2.0 and Open Host Controller

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all products and/or types are available in every country. Please check with an NEC Electronics

sales representative for availability and additional information.

144-pin plastic LQFP (Fine pitch) (20 × 20)

144-pin plastic FBGA (12 × 12)

USB 2.0 HOST CONTROLLER

The mark

PD720101 User’s Manual: S16336E

DATA SHEET

Package

shows major revised points.

PD720101 is integrated 3 host controller cores with PCI

MOS INTEGRATED CIRCUIT

Lead-free product

Remark

PD720101

2002

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