XR16C2850CJF Exar Corporation, XR16C2850CJF Datasheet

XR16C2850CJF

Manufacturer Part Number

XR16C2850CJF

Description

PLCC44

Manufacturer

Exar Corporation

Datasheet

1.XR16C2850CJF.pdf (51 pages)

Specifications of XR16C2850CJF

Date_code

03+

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NOVEMBER 2005

GENERAL DESCRIPTION

The XR16C2850

universal asynchronous receiver and transmitter

(UART). Enhanced features include 128 bytes of TX

and RX FIFOs, programmable TX and RX FIFO

trigger level, FIFO level counters, automatic (RTS/

CTS) hardware and (Xon/Xoff) software flow control,

automatic RS-485 half duplex direction control output

and data rates up to 6.25 Mbps at 5V and 8X

sampling clock. Onboard status registers provide the user

with operational status and data error flags. An internal

loopback capability allows system diagnostics. The 2850

has a full modem interface and can operate at 2.97V

to 5.5V and is pin-to-pin compatible to Exar’s

ST16C2550 and XR16C2750 except the 48-TQFP

package. The 2850 register set is compatible to the

industry standard ST16C2550 and is available in 48-

pin TQFP and 44-pin PLCC packages.

APPLICATIONS

•

Exar

OTE

IGURE

Portable Appliances

Telecommunication Network Routers

Ethernet Network Routers

Cellular Data Devices

Factory Automation and Process Controls

Corporation 48720 Kato Road, Fremont CA, 94538

1 Covered by U.S. Patent #5,649,122 and #5,949,787

RXRDYA#

RXRDYB#

TXRDYA#

TXRDYB#

HDCNTL#

1. XR16C2850 B

CLK8/16

CLKSEL

D7:D0

A2:A0

CSA#

CSB#

Reset

IOW#

IOR#

INTA

INTB

(2850) is an enhanced dual

LOCK

8-bit Data

Interface

Bus

IAGRAM

2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS

•

UART

(510) 668-7000

BRG

Regs

(same as Channel A)

Crystal Osc/Buffer

FEATURES

Added feature in devices with a top mark date code of

"F2 YYWW" and newer:

•

UART Channel B

UART Channel A

Pin-to-pin compatible and functionally compatible to

Exar’s ST16C2550 and XR16L2750 and TI’s

TL16C752B in the 48-TQFP package

Pin-alike Exar’s XR16L2750 and ST16C2550 48-

TQFP package but with additional CLK8/16,

CLKSEL and HDCNTL inputs

Two independent UART channels

Device Identification and Revision

Crystal oscillator or external clock input

Industrial and commercial temperature ranges

48-TQFP and 44-PLCC packages

TX & RX

128 Byte TX FIFO

128 Byte RX FIFO

■

5V tolerant inputs

0 ns address hold time (T

Up to 6.25 Mbps at 5V, and 4 Mbps at 3.3V

Transmit and Receive FIFOs of 128 bytes

Programmable TX and RX FIFO Trigger Levels

Transmit and Receive FIFO Level Counters

Automatic Hardware (RTS/CTS) Flow Control

Selectable Auto RTS Flow Control Hysteresis

Automatic Software (Xon/Xoff) Flow Control

Auto RS-485 Half-duplex Direction Control

Wireless Infrared (IrDA 1.0) Encoder/Decoder

Full modem interface

•

ENDEC

FAX (510) 668-7017

2.97V to 5.5V VCC

GND

TXA, RXA, DTRA#,

DSRA#, RTSA#,

DTSA#, CDA#, RIA#,

OP2A#

TXB, RXB, DTRB#,

DSRB#, RTSB#,

CTSB#, CDB#, RIB#,

OP2B#

XTAL1

XTAL2

•

www.exar.com

)

REV. 2.1.3

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