EP1C3T100I8 Altera Corporation, EP1C3T100I8 Datasheet

EP1C3T100I8

Manufacturer Part Number

EP1C3T100I8

Description

Manufacturer

Altera Corporation

Datasheets

1.EP1C12Q240I8.pdf (94 pages)

2.EP1C12Q240I8.pdf (74 pages)

Specifications of EP1C3T100I8

Package

TQFP

Date_code

09+

Available stocks

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Manufacturer

Quantity

Price

Company:

BOSTOCK HK LIMITED

Part Number:

EP1C3T100I8

Manufacturer:

ALTERA

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

EP1C3T100I8N

Manufacturer:

ALTERA

Quantity:

455

Company:

BOSTOCK HK LIMITED

Part Number:

EP1C3T100I8N

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ALTERA

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Introduction

Preliminary

Information

Features...

Note to

(1)

Altera Corporation

DS-CYCLONE-1.1

LEs

M4K RAM blocks (128

Total RAM bits

PLLs

Maximum user I/O pins

March 2003, ver. 1.1

Table 1. Cyclone Device Features

This parameter includes global clock pins.

Table

Feature

(1)

36 bits)

The Cyclone

0.13- m, all-layer copper SRAM process, with densities up to 20,060 logic

elements (LEs) and up to 288 Kbits of RAM. With features like phase-

locked loops (PLLs) for clocking and a dedicated double data rate (DDR)

interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory

requirements, Cyclone devices are a cost-effective solution for data-path

applications. Cyclone devices support various I/O standards, including

LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz,

32-bit peripheral component interconnect (PCI), for interfacing with and

supporting ASSP and ASIC devices. Altera also offers new low-cost serial

configuration devices to configure Cyclone devices.

2,910 to 20,060 LEs, see

Up to 294,912 RAM bits (36,864 bytes)

Supports configuration through low-cost serial configuration device

Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards

Support for 66-MHz, 32-bit PCI standard

Low speed (311 Mbps) LVDS I/O support

Up to two PLLs per device provide clock multiplication and phase

shifting

Up to eight global clock lines with six clock resources available per

logic array block (LAB) row

Support for external memory, including DDR SDRAM (133 MHz),

FCRAM, and single data rate (SDR) SDRAM

Support for multiple intellectual property (IP) cores, including

Altera MegaCore functions and Altera Megafunctions Partners

Program (AMPP

59,904

EP1C3

2,910

104

field programmable gate array family is based on a 1.5-V,

78,336

EP1C4

4,000

) megafunctions

301

Table 1

92,160

EP1C6

5,980

185

239,616

EP1C12

12,060

249

FPGA Family

Cyclone

Data Sheet

294,912

EP1C20

20,060

301

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