CY7C1471V33-133AXI Cypress Semiconductor Corporation., CY7C1471V33-133AXI Datasheet

CY7C1471V33-133AXI

Manufacturer Part Number

CY7C1471V33-133AXI

Description

Manufacturer

Cypress Semiconductor Corporation.

Datasheets

1.CY7C1471V33-133AXI.pdf (32 pages)

2.CY7C1471V33-133AXI.pdf (32 pages)

Specifications of CY7C1471V33-133AXI

Package

QFP

Date_code

09+

Current page: 1 of 32
Download datasheet (2Mb)

Cypress Semiconductor Corporation

Document #: 38-05288 Rev. *J

Features

Selection Guide

Note

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby Current

1. For best practice recommendations, refer to the Cypress application note

• No Bus Latency™ (NoBL™) architecture eliminates dead

• Supports up to 133 MHz bus operations with zero wait states

• Data is transferred on every clock

• Pin compatible and functionally equivalent to ZBT™ devices

• Internally self timed output buffer control to eliminate the

• Registered inputs for flow through operation

• Byte Write capability

• 3.3V/2.5V IO supply (V

• Fast clock-to-output times

• Clock Enable (CEN) pin to enable clock and suspend

• Synchronous self timed writes

• Asynchronous Output Enable (OE)

• CY7C1471V33, CY7C1473V33 available in

• Three Chip Enables (CE

• Automatic power down feature available using ZZ mode or

• IEEE 1149.1 JTAG Boundary Scan compatible

• Burst Capability — linear or interleaved burst order

• Low standby power

cycles between write and read cycles

need to use OE

— 6.5 ns (for 133-MHz device)

operation

JEDEC-standard Pb-free 100-Pin TQFP, Pb-free and

non-Pb-free 165-Ball FBGA package. CY7C1475V33

available in Pb-free and non-Pb-free 209-Ball FBGA

package

expansion

CE deselect

DDQ

, CE

)

, CE

Flow-Through SRAM with NoBL™ Architecture

) for simple depth

•

198 Champion Court

72-Mbit (2M x 36/4M x 18/1M x 72)

AN1064, SRAM System

Functional Description

The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are

3.3V, 2M x 36/4M x 18/1M x 72 synchronous flow through burst

SRAMs designed specifically to support unlimited true

back-to-back read or write operations without the insertion of

wait

CY7C1475V33 are equipped with the advanced No Bus

Latency (NoBL) logic required to enable consecutive read or

write operations with data being transferred on every clock

cycle. This feature dramatically improves the throughput of

data through the SRAM, especially in systems that require

frequent write-read transitions.

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. The clock input is qualified by

the Clock Enable (CEN) signal, which when deasserted

suspends operation and extends the previous clock

cycle.Maximum access delay from the clock rise is 6.5 ns

(133-MHz device).

Write operations are controlled by two or four Byte Write Select

(BW

with on-chip synchronous self timed write circuitry.

Three synchronous Chip Enables (CE

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. To avoid bus contention,

the output drivers are synchronously tri-stated during the data

portion of a write sequence.

133 MHz

) and a Write Enable (WE) input. All writes are conducted

305

120

6.5

•

states.

San Jose

Guidelines.

The

CA 95134-1709

CY7C1471V33,

117 MHz

275

120

8.5

[1]

CY7C1471V33

CY7C1473V33

CY7C1475V33

Revised July 04, 2007

CY7C1473V33

, CE

•

, CE

408-943-2600

Unit

) and an

and

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