ISPLSI2032E-180LJ44 Lattice Semiconductor Corp., ISPLSI2032E-180LJ44 Datasheet

ISPLSI2032E-180LJ44

Manufacturer Part Number

ISPLSI2032E-180LJ44

Description

Manufacturer

Lattice Semiconductor Corp.

Datasheets

1.ISPLSI2032E-180LJ44.pdf (14 pages)

2.ISPLSI2032E-180LJ44.pdf (14 pages)

Specifications of ISPLSI2032E-180LJ44

Package

PLCC-44

Date_code

10+

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LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

2032e_05

• SuperFAST HIGH DENSITY IN-SYSTEM

• HIGH PERFORMANCE E

• ispLSI OFFERS THE FOLLOWING ADDED FEATURES

• OFFERS THE EASE OF USE AND FAST SYSTEM

Features

PROGRAMMABLE LOGIC

— 1000 PLD Gates

— 32 I/O Pins, Two Dedicated Inputs

— 32 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

— Small Logic Block Size for Random Logic

— 100% Functionally and JEDEC Upward Compatible

—

— TTL Compatible Inputs and Outputs

— 5V Programmable Logic Core

— ispJTAG™ In-System Programmable via IEEE 1149.1

— User-Selectable 3.3V or 5V I/O (48-Pin Package Only)

— PCI Compatible Outputs (48-Pin Package Only)

— Open-Drain Output Option

— Electrically Erasable and Reprogrammable

— Non-Volatile

— Unused Product Term Shutdown Saves Power

— Increased Manufacturing Yields, Reduced Time-to-

— Reprogram Soldered Devices for Faster Prototyping

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Machines, Address Decoders, etc.

with ispLSI 2032 Devices

(JTAG) Test Access Port

Supports Mixed Voltage Systems

Market and Improved Product Quality

Logic and Structured Designs

Minimize Switching Noise

Interconnectivity

max = 225 MHz Maximum Operating Frequency

pd = 3.5 ns Propagation Delay

CMOS

TECHNOLOGY

The ispLSI 2032E is a High Density Programmable Logic

Device. The device contains 32 Registers, 32 Universal

I/O pins, two Dedicated Input Pins, three Dedicated

Clock Input Pins, one dedicated Global OE input pin and

a Global Routing Pool (GRP). The GRP provides com-

plete interconnectivity between all of these elements.

The ispLSI 2032E features 5V in-system programmabil-

ity and in-system diagnostic capabilities. The ispLSI

2032E offers non-volatile reprogrammability of the logic,

as well as the interconnect to provide truly reconfigurable

systems.

The basic unit of logic on the ispLSI 2032E device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. A7 (see Figure 1). There are a total of eight GLBs in the

ispLSI 2032E device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/Exclusive OR array, and four outputs which can

be configured to be either combinatorial or registered.

Inputs to the GLB come from the GRP and dedicated

inputs. All of the GLB outputs are brought back into the

GRP so that they can be connected to the inputs of any

GLB on the device.

The device also has 32 I/O cells, each of which is directly

connected to an I/O pin. Each I/O cell can be individually

Functional Block Diagram

Description

SuperFAST™ High Density PLD

GLB

ispLSI

Global Routing Pool

Logic

Array

In-System Programmable

(GRP)

D Q

2032E

November 2003

0139Bisp/2000

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