MM74HC573WMX Fairchild Semiconductor, MM74HC573WMX Datasheet

MM74HC573WMX

Manufacturer Part Number

MM74HC573WMX

Description

IC LATCH OCTAL D 3STATE 20-SOIC

Manufacturer

Fairchild Semiconductor

Series

74HCr

Datasheet

1.MM74HC573WMX.pdf (8 pages)

Specifications of MM74HC573WMX

Logic Type

D-Type Transparent Latch

Circuit

8:8

Output Type

Tri-State

Voltage - Supply

2 V ~ 6 V

Independent Circuits

Delay Time - Propagation

15ns

Current - Output High, Low

7.8mA, 7.8mA

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

20-SOIC (7.5mm Width)

Number Of Circuits

Logic Family

74HC

Polarity

Non-Inverting

Input Bias Current (max)

8 uA

High Level Output Current

- 7.8 mA

Low Level Output Current

7.8 mA

Propagation Delay Time

150 ns at 2 V, 30 ns at 4.5 V, 26 ns at 6 V

Supply Voltage (max)

6 V

Supply Voltage (min)

2 V

Maximum Operating Temperature

+ 85 C

Minimum Operating Temperature

- 40 C

Mounting Style

SMD/SMT

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Other names

MM74HC573WMX
MM74HC573WMXTR

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MM74HC573WM

MM74HC573SJ

MM74HC573MTC

MM74HC573N

MM74HC573

3-STATE Octal D-Type Latch

General Description

The MM74HC573 high speed octal D-type latches utilize

advanced silicon-gate P-well CMOS technology. They pos-

sess the high noise immunity and low power consumption

of standard CMOS integrated circuits, as well as the ability

to drive 15 LS-TTL loads. Due to the large output drive

capability and the 3-STATE feature, these devices are ide-

ally suited for interfacing with bus lines in a bus organized

system.

When the LATCH ENABLE(LE) input is HIGH, the Q out-

puts will follow the D inputs. When the LATCH ENABLE

goes LOW, data at the D inputs will be retained at the out-

puts until LATCH ENABLE returns HIGH again. When a

HIGH logic level is applied to the OUTPUT CONTROL OC

input, all outputs go to a HIGH impedance state, regardless

of what signals are present at the other inputs and the state

of the storage elements.

The 74HC logic family is speed, function and pinout com-

patible with the standard 74LS logic family. All inputs are

protected from damage due to static discharge by internal

diode clamps to V

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Order Number

Package Number

and ground.

MTC20

Top View

M20D

M20B

N20A

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

DS005212

Features

Truth Table

Typical propagation delay: 18 ns

Wide operating voltage range: 2 to 6 volts

Low input current: 1

Low quiescent current: 80

Compatible with bus-oriented systems

Output drive capability: 15 LS-TTL loads

LOW Level

High Impedance

Don't Care

HIGH Level

Level of output before steady-state input conditions were established.

Control

Output

Package Description

Enable

Latch

A maximum

A maximum (74HC Series)

September 1983

Revised May 2005

Data

www.fairchildsemi.com

Output

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MM74HC573WMX Summary of contents

Page 1

... Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Top View © 2005 Fairchild Semiconductor Corporation Features Typical propagation delay Wide operating voltage range volts ...

Page 2

Absolute Maximum Ratings (Note 2) Supply Voltage ( Input Voltage ( Output Voltage (V ) OUT Clamp Diode Current ( Output Current, per pin (I ) ...

Page 3

AC Electrical Characteristics q 5V Symbol Parameter Maximum Propagation Delay, Data to Q PHL PLH Maximum Propagation Delay PHL ...

Page 4

AC Electrical Characteristics Symbol Parameter Conditions C Maximum Output OUT Capacitance Note 5: C determines the no load dynamic power consumption www.fairchildsemi.com (Continued ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M20D 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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