IC OCTAL D TRANSP LATCH 20-SSOP

74HCT373DB,112

Manufacturer Part Number74HCT373DB,112
DescriptionIC OCTAL D TRANSP LATCH 20-SSOP
ManufacturerNXP Semiconductors
Series74HCT
74HCT373DB,112 datasheet
 

Specifications of 74HCT373DB,112

Logic TypeD-Type Transparent LatchPackage / Case20-SSOP
Circuit8:8Output TypeTri-State
Voltage - Supply4.5 V ~ 5.5 VIndependent Circuits1
Delay Time - Propagation33nsCurrent - Output High, Low6mA, 6mA
Operating Temperature-40°C ~ 125°CMounting TypeSurface Mount
Number Of Circuits8Logic FamilyHCT
PolarityNon-InvertingHigh Level Output Current- 6 mA
Low Level Output Current6 mAPropagation Delay Time14 ns
Supply Voltage (max)5.5 VSupply Voltage (min)4.5 V
Maximum Operating Temperature+ 125 CMinimum Operating Temperature- 40 C
Mounting StyleSMD/SMTLead Free Status / RoHS StatusLead free / RoHS Compliant
Other names568-2831-5
935174850112
  
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74HC373; 74HCT373
Octal D-type transparent latch; 3-state
Rev. 4 — 3 September 2010
1. General description
The 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible
with Low-power Schottky TTL. It is specified in compliance with JEDEC standard no. 7A.
The 74HC373; 74HCT373 is an octal D-type transparent latch featuring separate D-type
inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE)
input and an output enable (OE) input are common to all latches.
The 74HC373; 74HCT373 consists of eight D-type transparent latches with 3-state true
outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the
latches are transparent, i.e. a latch output will change state each time its corresponding
D input changes.
When LE is LOW the latches store the information that was present at the D inputs a
set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents
of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-
impedance OFF-state. Operation of the OE input does not affect the state of the latches.
The 74HC373; 74HCT373 is functionally identical to:
74HC563; 74HCT563: but inverted outputs and different pin arrangement
74HC573; 74HCT573: but different pin arrangement
2. Features and benefits
3-state non-inverting outputs for bus oriented applications
Common 3-state output enable input
Functionally identical to the 74HC563; 74HCT563 and 74HC573; 74HCT573
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Specified from −40 °C to +85 °C and from −40 °C to +125 °C
Product data sheet

74HCT373DB,112 Summary of contents

  • Page 1

    Octal D-type transparent latch; 3-state Rev. 4 — 3 September 2010 1. General description The 74HC373; 74HCT373 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL specified in compliance with JEDEC ...

  • Page 2

    ... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range −40 °C to +125 °C 74HC373N 74HCT373N −40 °C to +125 °C 74HC373D 74HCT373D −40 °C to +125 °C 74HC373DB 74HCT373DB −40 °C to +125 °C 74HC373PW 74HCT373PW −40 °C to +125 °C 74HC373BQ 74HCT373BQ 4 ...

  • Page 3

    ... NXP Semiconductors Fig 2. Logic symbol Fig 4. Logic diagram (one latch LATCH LATCH Fig 5. Logic diagram 74HC_HCT373 Product data sheet 001aae048 Fig LATCH LATCH All information provided in this document is subject to legal disclaimers. Rev. 4 — 3 September 2010 74HC373; 74HCT373 Octal D-type transparent latch; 3-state ...

  • Page 4

    ... NXP Semiconductors 5. Pinning information 5.1 Pinning 74HC373 74HCT373 GND 10 001aae046 Fig 6. Pin configuration DIP20, SO20, SSOP20 and TSSOP20 5.2 Pin description Table 2. Pin description Symbol OE Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 D0, D1, D2, D3, D4, D5, D6, D7 GND 74HC_HCT373 Product data sheet (1) The die substrate is attached to this pad using Fig 7 ...

  • Page 5

    ... NXP Semiconductors 6. Functional description 6.1 Function table [1] Table 3. Function table Operating mode Control OE Enable and read register L (transparent mode) Latch and read register L Latch register and disable H outputs [ HIGH voltage level HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; ...

  • Page 6

    ... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter V supply voltage CC V input voltage I V output voltage O T ambient temperature amb Δt/ΔV input transition rise and fall rate 9. Static characteristics Table 6. Static characteristics 74HC373 At recommended operating conditions ...

  • Page 7

    ... NXP Semiconductors Table 6. Static characteristics 74HC373 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter = −40 °C to +85 °C T amb V HIGH-level input voltage IH V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current ...

  • Page 8

    ... NXP Semiconductors Table 6. Static characteristics 74HC373 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V LOW-level output voltage OL I input leakage current I I OFF-state output current OZ I supply current CC Table 7. Static characteristics 74HCT373 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). ...

  • Page 9

    ... NXP Semiconductors Table 7. Static characteristics 74HCT373 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I OFF-state output current OZ I supply current CC ΔI additional supply current CC = −40 °C to +125 °C ...

  • Page 10

    ... NXP Semiconductors 10. Dynamic characteristics Table 8. Dynamic characteristics 74HC373 Voltages are referenced to GND (ground = 0 V); C Symbol Parameter = 25 °C T amb t propagation delay pd t enable time en t disable time dis t transition time t t pulse width W t set-up time su t hold time h C power dissipation capacitance ...

  • Page 11

    ... NXP Semiconductors Table 8. Dynamic characteristics 74HC373 Voltages are referenced to GND (ground = 0 V); C Symbol Parameter = −40 °C to +85 °C T amb t propagation delay pd t enable time en t disable time dis t transition time t t pulse width W t set-up time su t hold time h 74HC_HCT373 Product data sheet … ...

  • Page 12

    ... NXP Semiconductors Table 8. Dynamic characteristics 74HC373 Voltages are referenced to GND (ground = 0 V); C Symbol Parameter = −40 °C to +125 °C T amb t propagation delay pd t enable time en t disable time dis t transition time t t pulse width W t set-up time su 74HC_HCT373 Product data sheet …continued = 50 pF unless otherwise specified ...

  • Page 13

    ... NXP Semiconductors Table 8. Dynamic characteristics 74HC373 Voltages are referenced to GND (ground = 0 V); C Symbol Parameter t hold time h [ the same as t and PLH PHL [ the same as t and PZH PZL [ the same as t and t . dis PLZ PHZ [ the same as t and THL TLH ...

  • Page 14

    ... NXP Semiconductors Table 9. Dynamic characteristics 74HCT373 Voltages are referenced to GND (ground = 0 V); C Symbol Parameter = −40 °C to +85 °C T amb t propagation delay pd t enable time en t disable time dis t transition time t t pulse width W t set-up time su t hold time h = −40 °C to +125 °C ...

  • Page 15

    ... NXP Semiconductors Table 9. Dynamic characteristics 74HCT373 Voltages are referenced to GND (ground = 0 V); C Symbol Parameter t hold time [ the same as t and PLH PHL [ the same as t and PZH PZL [ the same as t and t . dis PLZ PHZ [ the same as t and THL TLH ...

  • Page 16

    ... NXP Semiconductors OE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in Fig 10. 3-state enable and disable time Measurement points are given in Fig 11. Set-up and hold time data input (Dn) to latch enable input (LE) Table 10. Measurement points Type 74HC373 74HCT373 74HC_HCT373 ...

  • Page 17

    ... NXP Semiconductors negative Test data is given in Table Definitions test circuit Termination resistance should be equal to output impedance Load capacitance including jig and probe capacitance Load resistor Test selection switch Fig 12. Test circuit for measuring switching times Table 11. Test data Type Input V I 74HC373 ...

  • Page 18

    ... NXP Semiconductors 12. Package outline DIP20: plastic dual in-line package; 20 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

  • Page 19

    ... NXP Semiconductors SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 mm 2.65 0.25 0.1 2.25 0.012 0.096 inches 0.1 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...

  • Page 20

    ... NXP Semiconductors SSOP20: plastic shrink small outline package; 20 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT339-1 Fig 15. Package outline SOT339-1 (SSOP20) ...

  • Page 21

    ... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

  • Page 22

    ... NXP Semiconductors DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm terminal 1 index area terminal 1 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0. 0.2 0.00 0.18 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

  • Page 23

    ... Data sheet status Product data sheet The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Figure 5 changed: inversion sign added to the output buffers. ...

  • Page 24

    ... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...

  • Page 25

    ... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16. Contact information For more information, please visit: For sales office addresses, please send an email to: 74HC_HCT373 Product data sheet 15 ...

  • Page 26

    ... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Functional description . . . . . . . . . . . . . . . . . . . 5 6.1 Function table . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 10 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 12 Package outline ...