M74HC573RM13TR STMicroelectronics, M74HC573RM13TR Datasheet

IC LATCH OCTAL D-TYPE 20-SOIC

M74HC573RM13TR

Manufacturer Part Number
M74HC573RM13TR
Description
IC LATCH OCTAL D-TYPE 20-SOIC
Manufacturer
STMicroelectronics
Series
74HCr
Datasheet

Specifications of M74HC573RM13TR

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
2 V ~ 6 V
Independent Circuits
1
Delay Time - Propagation
12ns
Current - Output High, Low
7.8mA, 7.8mA
Operating Temperature
-55°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
20-SOIC (7.5mm Width)
Number Of Circuits
8
Logic Family
74HC
Polarity
Non-Inverting
Input Bias Current (max)
4 uA
High Level Output Current
- 7.8 mA
Low Level Output Current
32 mA
Propagation Delay Time
150 ns at 2 V, 30 ns at 4.5 V, 26 ns at 6 V
Supply Voltage (max)
6 V
Supply Voltage (min)
2 V
Maximum Operating Temperature
+ 125 C
Minimum Operating Temperature
- 55 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-1876-2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M74HC573RM13TR
Manufacturer:
PIONEER
Quantity:
560
Part Number:
M74HC573RM13TR
Manufacturer:
ST
0
DESCRIPTION
The M74HC573 is an high speed CMOS OCTAL
LATCH WITH 3-STATE OUTPUTS fabricated
with silicon gate C
This 8-BIT D-Type latches is controlled by a latch
enable input (LE) and output enable input (OE).
While the LE input is held at a high level, the Q
outputs will follow the data input precisely. When
LE is taken low, the Q outputs will be latched
precisely at the logic level of D input data.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
HIGH SPEED:
t
LOW POWER DISSIPATION:
I
HIGH NOISE IMMUNITY:
V
SYMMETRICAL OUTPUT IMPEDANCE:
|I
BALANCED PROPAGATION DELAYS:
t
WIDE OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 573
PD
CC
PLH
OH
NIH
CC
= 13ns (TYP.) at V
= 4 A(MAX.) at T
| = I
(OPR) = 2V to 6V
= V
t
PHL
OL
NIL
= 6mA (MIN)
= 28 % V
2
MOS technology.
A
CC
CC
=25°C
(MIN.)
= 6V
WITH 3 STATE OUTPUT NON INVERTING
ORDER CODES
While the OE input is at low level, the eight outputs
will be in a normal logic state (high or low logic
level) and while is at high level the outputs will be
in a high impedance state.
The 3-State output configuration and the wide
choice of outline make bus organized system
simple.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
PACKAGE
TSSOP
SOP
DIP
DIP
OCTAL D-TYPE LATCH
M74HC573M1R
M74HC573B1R
TUBE
SOP
M74HC573
M74HC573RM13TR
M74HC573TTR
T & R
TSSOP
1/12

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M74HC573RM13TR Summary of contents

Page 1

... The 3-State output configuration and the wide choice of outline make bus organized system simple. All inputs are equipped with protection circuits against static discharge and transient excess voltage. M74HC573 OCTAL D-TYPE LATCH DIP SOP TUBE T & R M74HC573B1R M74HC573M1R M74HC573RM13TR M74HC573TTR TSSOP 1/12 ...

Page 2

M74HC573 INPUT AND OUTPUT EQUIVALENT CIRCUIT TRUTH TABLE Don’t Care Z: High Impedance (*): Q Outputs are latched at the time when the LE input is taken low logic level. LOGIC DIAGRAM 2/12 PIN ...

Page 3

ABSOLUTE MAXIMUM RATINGS Symbol V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Current ...

Page 4

M74HC573 DC SPECIFICATIONS Symbol Parameter V V High Level Input IH Voltage V Low Level Input IL Voltage V High Level Output OH Voltage V Low Level Output OL Voltage I Input Leakage I Current I High Impedance OZ Output ...

Page 5

AC ELECTRICAL CHARACTERISTICS (C Symbol Parameter Output Transition TLH THL Time t t Propagation Delay PLH PHL Time ( Propagation Delay PLH PHL Time ( High Impedance PZL PZH ...

Page 6

M74HC573 CAPACITIVE CHARACTERISTICS Symbol Parameter C Input Capacitance IN Output C OUT Capacitance C Power Dissipation PD Capacitance (note defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current ...

Page 7

WAVEFORM PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) M74HC573 7/12 ...

Page 8

M74HC573 WAVEFORM 3: PROPAGATION DELAY TIMES (f=1MHz; 50% duty cycle) 8/12 ...

Page 9

Plastic DIP-20 (0.25) MECHANICAL DATA mm. DIM. MIN. a1 0.254 B 1. 22. TYP MAX. MIN. 0.010 1.65 0.055 0.45 0.25 25.4 8.5 2.54 7.1 3.93 3.3 1.34 M74HC573 inch ...

Page 10

M74HC573 DIM. MIN 0 0. 12.60 E 10. 7. 10/12 SO-20 MECHANICAL DATA mm. TYP MAX. 2.65 0.2 2.45 0.49 0.32 0.5 45° (typ.) ...

Page 11

TSSOP20 MECHANICAL DATA DIM. MIN 0.05 A2 0.8 b 0.19 c 0.09 D 6.4 E 6.2 E1 4.3 e 0.65 BSC K 0° PIN 1 IDENTIFICATION 1 mm. TYP MAX. MIN. 1.2 ...

Page 12

... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied ...

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