74LCX373TTR STMicroelectronics, 74LCX373TTR Datasheet

IC LATCH OCTAL D 3STATE 20-TSSOP

74LCX373TTR

Manufacturer Part Number
74LCX373TTR
Description
IC LATCH OCTAL D 3STATE 20-TSSOP
Manufacturer
STMicroelectronics
Series
74LCXr
Datasheet

Specifications of 74LCX373TTR

Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
2 V ~ 3.6 V
Independent Circuits
1
Delay Time - Propagation
1.5ns
Current - Output High, Low
24mA, 24mA
Operating Temperature
-55°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-7099-2
74LCX373TTR

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Quantity
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74LCX373TTR
Manufacturer:
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Quantity:
20 000
Part Number:
74LCX373TTR
Manufacturer:
STM
Quantity:
14 768
DESCRIPTION
The 74LCX373 is a low voltage CMOS OCTAL
D-TYPE
NON-INVERTING fabricated with sub-micron
silicon gate and double-layer metal wiring C
technology. It is ideal for low power and high
speed 3.3V applications; it can be interfaced to 5V
signal environment for both inputs and outputs.
These 8 bit D-Type latch are controlled by a latch
Figure 1: Pin Connection And IEC Logic Symbols
September 2004
5V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED:
t
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
PCI BUS LEVELS GUARANTEED AT 24 mA
BALANCED PROPAGATION DELAYS:
t
OPERATING VOLTAGE RANGE:
V
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
PD
PLH
OH
CC
= 8.0 ns (MAX.) at V
| = I
(OPR) = 2.0V to 3.6V (1.5V Data
t
PHL
LATCH
OL
= 24mA (MIN) at V
OCTAL D-TYPE LATCH NON-INVERTING (3-STATE)
with
WITH 5V TOLERANT INPUTS AND OUTPUTS
3
CC
= 3V
STATE
CC
= 3V
OUTPUT
2
MOS
Table 1: Order Codes
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input. When the LE is
taken low, the Q outputs will be latched precisely
at the logic level of D input data. While the (OE)
input is low, the 8 outputs will be in a normal logic
state (high or low logic level) and while (OE) is in
high level, the outputs will be in a high impedance
state.
It has same speed performance at 3.3V than 5V
AC/ACT family, combined with a lower power
consumption.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
PACKAGE
TSSOP
SOP
SOP
74LCX373
Rev. 5
74LCX373MTR
74LCX373TTR
TSSOP
T & R
1/13

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74LCX373TTR Summary of contents

Page 1

... OUTPUT AC/ACT family, combined with a lower power 2 consumption. MOS All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage. 74LCX373 SOP TSSOP PACKAGE T & R SOP 74LCX373MTR TSSOP 74LCX373TTR Rev. 5 1/13 ...

Page 2

Figure 2: Input And Output Equivalent Circuit Table 2: Pin Description PIN N° SYMBOL NAME AND FUNCTION State Output Enable Input (Active LOW 12 Data Inputs 15, 16,19 3, ...

Page 3

Table 4: Absolute Maximum Ratings Symbol V Supply Voltage Input Voltage Output Voltage (OFF State Output Voltage (High or Low State) (note Input Diode Current IK I ...

Page 4

Table 6: DC Specifications Symbol Parameter V High Level Input IH Voltage V Low Level Input IL Voltage V High Level Output OH Voltage V Low Level Output OL Voltage I Input Leakage I Current I Power Off Leakage ...

Page 5

Table 8: AC Electrical Characteristics Symbol Parameter t t Propagation Delay PLH PHL Time ( Propagation Delay PLH PHL Time ( Output Enable Time PZL PZH to HIGH and LOW level t ...

Page 6

Figure 4: Test Circuit PLH PHL PZL PLZ PZH PHZ equivalent (includes jig and probe capacitance 500 or equivalent L ...

Page 7

Figure 6: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle) Figure 7: Waveform - Propagation Delay Time (f=1MHz; 50% duty cycle) 74LCX373 7/13 ...

Page 8

DIM. MIN. A 2.35 A1 0.1 B 0.33 C 0.23 D 12. 10.00 h 0.25 L 0.4 k 0° ddd 8/13 SO-20 MECHANICAL DATA mm. TYP MAX. 2.65 0.30 0.51 0.32 13.00 7.6 1.27 10.65 ...

Page 9

TSSOP20 MECHANICAL DATA DIM. MIN 0.05 A2 0.8 b 0.19 c 0.09 D 6.4 E 6 0˚ PIN 1 IDENTIFICATION 1 mm. TYP MAX. 1.2 0.15 1 1.05 ...

Page 10

DIM. MIN 12 10.8 Bo 13.2 Ko 3.1 Po 3.9 P 11.9 10/13 Tape & Reel SO-20 MECHANICAL DATA mm. TYP MAX. 330 13.2 30.4 11 13.4 3.3 4.1 12.1 inch ...

Page 11

Tape & Reel TSSOP20 MECHANICAL DATA DIM. MIN 12 6.8 Bo 6.9 Ko 1.7 Po 3.9 P 11.9 mm. TYP MAX. 330 13.2 0.504 0.795 2.362 22.4 7 0.268 7.1 0.272 1.9 ...

Page 12

Table 10: Revision History Date Revision 15-Sep-2004 5 12/13 Description of Changes Ordering Codes Revision - pag. 1. ...

Page 13

... No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics ...

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