IDT74LVC16373APAG IDT, Integrated Device Technology Inc, IDT74LVC16373APAG Datasheet
IDT74LVC16373APAG
Manufacturer Part Number
IDT74LVC16373APAG
Description
IC TRANSP LATCH 16BIT D 48-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
74LVCr
Type
D-Typer
Datasheet
1.IDT74LVC16373APAG.pdf
(6 pages)
Specifications of IDT74LVC16373APAG
Logic Type
D-Type Transparent Latch
Circuit
8:8
Output Type
Tri-State
Voltage - Supply
2.3 V ~ 3.6 V
Independent Circuits
2
Delay Time - Propagation
2.1ns
Current - Output High, Low
24mA, 24mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Logic Family
LVC
Number Of Bits
16
Number Of Elements
2
Latch Mode
Transparent
Polarity
Non-Inverting
Technology
CMOS
Package Type
TSSOP
Propagation Delay Time
6.3ns
Operating Supply Voltage (typ)
3.3V
High Level Output Current
-24mA
Low Level Output Current
24mA
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74LVC16373APAG
800-1661
800-1661-5
800-1661
800-1661
800-1661-5
800-1661
FEATURES:
• Typical t
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
• V
• V
• CMOS power levels (0.4μ μ μ μ μ W typ. static)
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
• Available in SSOP and TSSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
© 2006 Integrated Device Technology, Inc.
1
1
IDT74LVC16373A
3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH
1
OE
LE
machine model (C = 200pF, R = 0)
D
CC
CC
1
= 3.3V ± 0.3V, Normal Range
= 2.7V to 3.6V, Extended Range
INDUSTRIAL TEMPERATURE RANGE
48
47
1
SK(o)
(Output Skew) < 250ps
TO SEVEN OTHER CHANNELS
D
C
Q
3.3V CMOS 16-BIT
TRANSPARENT D-TYPE
LATCH WITH 3-STATE OUTPUTS
AND 5 VOLT TOLERANT I/O
2
1
Q
1
1
DESCRIPTION:
dual metal CMOS technology. This high-speed, low-power latch is ideal
for temporary storage of data. The LVC16373A can be used for implement-
ing memory address latches, I/O ports, and bus drivers. The Output Enable
and Latch Enable controls are organized to operate each device as two 8-
bit latches or one 16-bit latch. Flow-through organization of signal pins
simplifies layout. All inputs are designed with hysteresis for improved noise
margin.
This feature allows the use of this device as a translator in a mixed 3.3V/
5V supply system.
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
2
2
2
OE
The LVC16373A 16-bit transparent D-type latch is built using advanced
All pins of the LVC16373A can be driven from either 3.3V or 5V devices.
The LVC16373A has been designed with a
LE
D
1
36
24
25
TO SEVEN OTHER CHANNELS
INDUSTRIAL TEMPERATURE RANGE
D
C
IDT74LVC16373A
Q
±
24mA output driver. This
OCTOBER 2008
DSC-4624/5
13
2
Q
1
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IDT74LVC16373APAG Summary of contents
Page 1
IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH FEATURES: • Typical t (Output Skew) < 250ps SK(o) • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF • 3.3V ± ...
Page 2
IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH PIN CONFIGURATION GND ...
Page 3
IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Operating Condition –40°C to +85°C A Symbol Parameter V Input HIGH Voltage Level IH V Input LOW Voltage Level ...
Page 4
IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH OPERATING CHARACTERISTICS, V Symbol Parameter C Power Dissipation Capacitance per Latch Outputs enabled PD C Power Dissipation Capacitance per Latch Outputs disabled PD SWITCHING CHARACTERISTICS Symbol Parameter t Propagation Delay PLH t xDx ...
Page 5
IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS (1) (1) Symbol V = 3.3V±0. 2. LOAD V 2.7 2 1.5 1 300 300 LZ ...
Page 6
IDT74LVC16373A 3.3V CMOS 16-BIT TRANSPARENT D-TYPE LATCH ORDERING INFORMATION LVC Bus-Hold Family Temp. Range CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 XX XXXX Device Type Package PV PVG PA PAG 373A 16 Blank ...