LS373

Manufacturer Part NumberLS373
ManufacturerTexas Instruments, Inc.
LS373 datasheet
 


Specifications of LS373

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OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
Choice of Eight Latches or Eight D-Type
Flip-Flops in a Single Package
3-State Bus-Driving Outputs
Full Parallel Access for Loading
Buffered Control Inputs
Clock-Enable Input Has Hysteresis to
Improve Noise Rejection (’S373 and ’S374)
P-N-P Inputs Reduce DC Loading on Data
Lines (’S373 and ’S374)
description
These 8-bit registers feature 3-state outputs
designed specifically for driving highly capacitive
or
relatively
low-impedance
high-impedance
3-state
and
high-logic-level drive provide these registers with
the capability of being connected directly to and
driving the bus lines in a bus-organized system
without need for interface or pullup components.
These devices are particularly attractive for
implementing
buffer
registers,
bidirectional bus drivers, and working registers.
The eight latches of the ’LS373 and ’S373 are
transparent D-type latches, meaning that while
the enable (C or CLK) input is high, the Q outputs
follow the data (D) inputs. When C or CLK is taken
low, the output is latched at the level of the data
that was set up.
The eight flip-flops of the ’LS374 and ’S374 are
edge-triggered D-type flip-flops. On the positive
transition of the clock, the Q outputs are set to the
logic states that were set up at the D inputs.
Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design
as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered
output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic
levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly.
OC does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new
data can be entered, even while the outputs are off.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
SN54LS373, SN54LS374, SN54S373,
SN54S374 . . . J OR W PACKAGE
SN74LS373, SN74S374 . . . DW, N, OR NS PACKAGE
SN74LS374 . . . DB, DW, N, OR NS PACKAGE
SN74S373 . . . DW OR N PACKAGE
loads.
The
increased
† C for ’LS373 and ’S373; CLK for ’LS374 and ’S374.
SN54LS373, SN54LS374, SN54S373,
SN54S374 . . . FK PACKAGE
I/O
ports,
2D
2Q
3Q
3D
4D
† C for ’LS373 and ’S373; CLK for ’LS374 and ’S374.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
(TOP VIEW)
OC
V
1
20
CC
1Q
2
19
8Q
1D
3
18
8D
2D
4
17
7D
2Q
5
16
7Q
3Q
6Q
6
15
3D
7
14
6D
4D
8
13
5D
4Q
9
12
5Q
GND
10
11
C
(TOP VIEW)
3 2 1 20 19
8D
18
4
7D
5
17
7Q
6
16
6Q
7
15
6D
14
8
9 10 11 12 13
Copyright
2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
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