74LVT16373MTD Fairchild Semiconductor, 74LVT16373MTD Datasheet

74LVT16373MTD

Manufacturer Part Number

74LVT16373MTD

Description

IC LATCH TRANSP 16BIT 48TSSOP

Manufacturer

Fairchild Semiconductor

Series

74LVTr

Datasheet

1.74LVTH16373MTDX.pdf (8 pages)

Specifications of 74LVT16373MTD

Logic Type

D-Type Transparent Latch

Circuit

8:8

Output Type

Tri-State

Voltage - Supply

2.7 V ~ 3.6 V

Independent Circuits

Delay Time - Propagation

1.5ns

Current - Output High, Low

32mA, 64mA

Operating Temperature

-40°C ~ 85°C

Mounting Type

Surface Mount

Package / Case

48-TSSOP

Number Of Circuits

Logic Family

74LVT

Polarity

Non-Inverting

High Level Output Current

- 32 mA

Low Level Output Current

64 mA

Propagation Delay Time

4.3 ns at 2.7 V, 3.9 ns at 3.3 V

Supply Voltage (max)

3.6 V

Supply Voltage (min)

2.7 V

Maximum Operating Temperature

+ 85 C

Minimum Operating Temperature

- 40 C

Mounting Style

SMD/SMT

Supply Current

5 mA

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

74LVT16373MTDX

Manufacturer:

ATMEL

Quantity:

103

Company:

Meier Automation Equipment Co., Limited

Part Number:

74LVT16373MTDX

Manufacturer:

FAIRCHILD/仙童

Quantity:

20 000

Current page: 1 of 8
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74LVT16373GX

(Note 1)

74LVT16373MEA

(Note 2)

74LVT16373MTD

(Note 2)

74LVTH16373GX

(Note 1)

74LVTH16373MEA

(Note 2)

74LVTH16373MTD

(Note 2)

74LVT16373 • 74LVTH16373

Low Voltage 16-Bit Transparent Latch

with 3-STATE Outputs

General Description

The LVT16373 and LVTH16373 contain sixteen non-invert-

ing latches with 3-STATE outputs and is intended for bus

oriented applications. The device is byte controlled. The

flip-flops appear transparent to the data when the Latch

Enable (LE) is HIGH. When LE is LOW, the data that meets

the setup time is latched. Data appears on the bus when

the Output Enable (OE) is LOW. When OE is HIGH, the

outputs are in a high impedance state.

The LVTH16373 data inputs include bushold, eliminating

the need for external pull-up resistors to hold unused

inputs.

These latches are designed for low-voltage (3.3V) V

applications, but with the capability to provide a TTL inter-

face to a 5V environment. The LVT16373 and LVTH16373

are fabricated with an advanced BiCMOS technology to

achieve high speed operation similar to 5V ABT while

maintaining a low power dissipation.

Ordering Code:

Note 1: BGA package available in Tape and Reel only.

Note 2: Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Order Number

Package Number

(Preliminary)

BGA54A

MS48A

MTD48

MS48A

MTD48

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[TAPE and REEL]

48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide

48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS012021

Features

Input and output interface capability to systems at

5V V

Bushold data inputs eliminate the need for external

pull-up resistors to hold unused inputs (74LVTH16373),

also available without bushold feature (74LVT16373)

Live insertion/extraction permitted

Power Up/Power Down high impedance provides

glitch-free bus loading

Outputs source/sink

Functionally compatible with the 74 series 16373

Latch-up performance exceeds 500 mA

ESD performance:

Human-body model

Machine model

Charged-device model

Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA) (Preliminary)

Package Description

200V

32 mA/

2000V

1000V

January 1999

Revised June 2005

64 mA

www.fairchildsemi.com

Related parts for 74LVT16373MTD

74LVT16373MTD Summary of contents

Page 1

... REEL] 74LVT16373MEA MS48A 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide (Note 2) 74LVT16373MTD MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide (Note 2) 74LVTH16373GX BGA54A 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide ...

Page 2

Connection Diagrams Pin Assignment for SSOP and TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Names Description OE Output Enable Input (Active LOW Latch Enable Input n I –I Inputs –O ...

Page 3

Functional Description The LVT16373 and LVTH16373 contain sixteen D-type latches with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but inde- pendent of the other. Control pins can be shorted together to obtain full 16-bit ...

Page 4

Absolute Maximum Ratings Symbol Parameter V Supply Voltage Input Voltage Output Voltage Input Diode Current Output Diode Current Output Current Supply Current ...

Page 5

DC Electrical Characteristics Symbol Parameter I Power Supply Current CCH I Power Supply Current CCL I Power Supply Current CCZ I Power Supply Current CCZ ' I Increase in Power Supply Current CC (Note 8) Note 5: Applies to ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide www.fairchildsemi.com Package Number BGA54A Preliminary 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 7 www.fairchildsemi.com ...

Page 8

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves ...

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