PIC16F684-ISL

Manufacturer Part NumberPIC16F684-ISL
ManufacturerMicrochip Technology Inc.
PIC16F684-ISL datasheets
 


Specifications of PIC16F684-ISL

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PIC16F684
FIGURE 12-10:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
OSC1
(4)
CLKOUT
INT pin
INTF flag
(INTCON<1>)
GIE bit
(INTCON<7>)
Instruction Flow
PC
PC
PC + 1
Instruction
Inst(PC + 1)
Inst(PC) = Sleep
Fetched
Instruction
Sleep
Inst(PC – 1)
Executed
Note 1:
XT, HS or LP Oscillator mode assumed.
2:
T
= 1024 T
(drawing not to scale). This delay does not apply to EC and RC Oscillator modes.
OST
OSC
3:
GIE = ‘1’ assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = ‘0’, execution will continue in-line.
4:
CLKOUT is not available in XT, HS, LP or EC oscillator modes, but shown here for timing reference.
12.8
Code Protection
If
the
code
protection
bit(s)
have
programmed, the on-chip program memory can be
read out using ICSP
for verification purposes.
Note:
The entire data EEPROM and Flash
program memory will be erased when the
code protection is turned off. See the
“PIC12F6XX/16F6XX Memory Program-
ming Specification” (DS41204) for more
information.
12.9
ID Locations
Four memory locations (2000h-2003h) are designated
as ID locations where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution but are
readable and writable during Program/Verify mode.
Only the Least Significant 7 bits of the ID locations are
used.
12.10 In-Circuit Serial Programming
The PIC16F684 microcontrollers can be serially
programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for:
• power
• ground
• programming voltage
DS41202C-page 108
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OST (2)
T
(3)
Interrupt Latency
Processor in
Sleep
PC + 2
PC + 2
PC + 2
Inst(PC + 2)
Inst(PC + 1)
Dummy Cycle
This allows customers to manufacture boards with
unprogrammed devices and then program the micro-
not
been
controller just before shipping the product. This also
allows the most recent firmware or a custom firmware
to be programmed.
The device is placed into a Program/Verify mode by
holding the RA0 and RA1 pins low, while raising the
MCLR (V
) pin from V
PP
16F6XX
Memory
(DS41204) for more information. RA0 becomes the
programming data and RA1 becomes the programming
clock. Both RA0 and RA1 are Schmitt Trigger inputs in
this mode.
After Reset, to place the device into Program/Verify
mode, the Program Counter (PC) is at location 00h. A
6-bit command is then supplied to the device.
Depending on the command, 14 bits of program data
are then supplied to or from the device, depending on
whether the command was a load or a read. For
complete details of serial programming, please refer to
the
“PIC12F6XX/16F6XX
Specification” (DS41204).
A typical In-Circuit Serial Programming connection is
shown in Figure 12-11.
Preliminary
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy Cycle
Inst(0004h)
to V
. See the “PIC12F6XX/
IL
IHH
Programming
Specification”
Memory
Programming
 2004 Microchip Technology Inc.