PIC16F684-ISL

Manufacturer Part NumberPIC16F684-ISL
ManufacturerMicrochip Technology Inc.
PIC16F684-ISL datasheets
 


Specifications of PIC16F684-ISL

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DECFSZ
Decrement f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Operands:
0
f
127
d
[0,1]
Operation:
(f) - 1
(destination);
skip if result = 0
Status Affected:
None
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
result is ‘0’, then a NOP is
executed instead, making it a
2-cycle instruction.
GOTO
Unconditional Branch
Syntax:
[ label ]
GOTO k
Operands:
0
k
2047
Operation:
k
PC<10:0>
PCLATH<4:3>
PC<12:11>
Status Affected:
None
Description:
GOTO is an unconditional branch.
The eleven-bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded from
PCLATH<4:3>. GOTO is a
two-cycle instruction.
INCF
Increment f
Syntax:
[ label ]
INCF f,d
Operands:
0
f
127
d
[0,1]
Operation:
(f) + 1
(destination)
Status Affected:
Z
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
 2004 Microchip Technology Inc.
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ]
Operands:
0
f
d
[0,1]
Operation:
(f) + 1
skip if result = 0
Status Affected:
None
Description:
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
If the result is ‘1’, the next
instruction is executed. If the
result is ‘0’, a NOP is executed
instead, making it a 2-cycle
instruction.
IORLW
Inclusive OR literal with W
Syntax:
[ label ]
Operands:
0
k
Operation:
(W) .OR. k
Status Affected:
Z
Description:
The contents of the W register are
OR’ed with the eight-bit literal ‘k’.
The result is placed in the
W register.
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Operands:
0
f
d
[0,1]
Operation:
(W) .OR. (f)
Status Affected:
Z
Description:
Inclusive OR the W register with
register ‘f’. If ‘d’ is ‘0’, the result is
placed in the W register. If ‘d’ is
‘1’, the result is placed back in
register ‘f’.
Preliminary
PIC16F684
INCFSZ f,d
127
(destination),
IORLW k
255
(W)
IORWF
f,d
127
(destination)
DS41202C-page 115