PIC16F684-ISL Microchip Technology Inc., PIC16F684-ISL Datasheet - Page 35
Manufacturer Part Number
Microchip Technology Inc.
Specifications of PIC16F684-ISL
Each of the PORTA pins is individually configurable as
an interrupt-on-change pin. Control bits IOCAx enable
or disable the interrupt function for each pin. Refer to
Register 4-4. The interrupt-on-change is disabled on a
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTA. The ‘mismatch’ outputs of the last read are
OR’d together to set the PORTA Change Interrupt Flag
bit (RAIF) in the INTCON register (Register 2-3).
IOCA – INTERRUPT-ON-CHANGE PORTA REGISTER (ADDRESS: 96h)
Unimplemented: Read as ‘0’
IOCA<5:0>: Interrupt-on-change PORTA Control bit
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
Note 1: Global Interrupt Enable (GIE) must be enabled for individual interrupts to be
2: IOCA<5:4> always reads ‘1’ in XT, HS and LP OSC modes.
R = Readable bit
-n = Value at POR
2004 Microchip Technology Inc.
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, clears the
Any read or write of PORTA. This will end the
mismatch condition, then,
Clear the flag bit RAIF.
A mismatch condition will continue to set flag bit RAIF.
Reading PORTA will end the mismatch condition and
allow flag bit RAIF to be cleared. The latch holding the
last read value is not affected by a MCLR nor BOD
Reset. After these resets, the RAIF flag will continue to
be set if a mismatch is present.
If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RAIF
interrupt flag may not get set.
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown