PIC16F684-ISL

Manufacturer Part NumberPIC16F684-ISL
ManufacturerMicrochip Technology Inc.
PIC16F684-ISL datasheets
 


Specifications of PIC16F684-ISL

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Page 66/164

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PIC16F684
9.1.4
CONVERSION CLOCK
The A/D conversion cycle requires 11 T
of the conversion clock is software selectable via the
ADCS bits (ADCON1<6:4>). There are seven possible
clock options:
• F
/2
OSC
• F
/4
OSC
• F
/8
OSC
TABLE 9-1:
T
VS. DEVICE OPERATING FREQUENCIES
AD
A/D Clock Source (T
)
AD
Operation
ADCS2:ADCS0
2 T
000
OSC
4 T
100
OSC
8 T
OSC
001
16 T
OSC
101
32 T
010
OSC
64 T
110
OSC
A/D RC
x11
Legend: Shaded cells are outside of recommended range.
Note 1:
The A/D RC source has a typical T
2:
These values violate the minimum required T
3:
For faster conversion times, the selection of another clock source is recommended.
4:
When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the
conversion will be performed during Sleep.
9.1.5
STARTING A CONVERSION
The A/D conversion is initiated by setting the
GO/DONE bit (ADCON0<1>). When the conversion is
complete, the A/D module:
• Clears the GO/DONE bit
• Sets the ADIF flag (PIR1<6>)
• Generates an interrupt (if enabled)
FIGURE 9-2:
A/D CONVERSION T
T
to T
T
1
T
2
T
CY
AD
AD
AD
AD
b9
b8
Conversion Starts
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
Set GO bit
DS41202C-page 64
• F
/16
OSC
• F
/32
OSC
. The source
AD
• F
/64
OSC
• F
(dedicated internal oscillator)
RC
For correct conversion, the A/D conversion clock
(1/T
) must be selected to ensure a minimum T
AD
1.6 s. Table 9-1 shows a few T
selected frequencies.
Device Frequency
20 MHz
5 MHz
(2)
(2)
100 ns
400 ns
(2)
(2)
200 ns
800 ns
(2)
400 ns
1.6 s
(2)
800 ns
3.2 s
1.6 s
6.4 s
(3)
3.2 s
12.8 s
(1,4)
(1,4)
2-6 s
2-6 s
time of 4 s for V
> 3.0V.
AD
DD
time.
AD
If the conversion must be aborted, the GO/DONE bit
can be cleared in software. The ADRESH:ADRESL
registers will not be updated with the partially complete
A/D
conversion
ADRESH:ADRESL registers will retain the value of the
previous conversion. After an aborted conversion, a
2 T
delay is required before another acquisition can
AD
be initiated. Following the delay, an input acquisition is
automatically started on the selected channel.
Note:
The GO/DONE bit should not be set in the
same instruction that turns on the A/D.
CYCLES
AD
3
T
4
T
5
T
6
T
7
T
8
AD
AD
AD
AD
AD
b7
b6
b5
b4
b3
ADRESH and ADRESL registers are Loaded,
GO bit is Cleared,
ADIF bit is Set,
Holding Capacitor is Connected to Analog Input
Preliminary
AD
calculations for
AD
4 MHz
1.25 MHz
(2)
500 ns
1.6 s
(2)
1.0 s
3.2 s
2.0 s
6.4 s
(3)
4.0 s
12.8 s
(3)
(3)
8.0 s
25.6 s
(3)
(3)
16.0 s
51.2 s
(1,4)
(1,4)
2-6 s
2-6 s
sample.
Instead,
the
T
9
T
10 T
11
AD
AD
AD
b2
b1
b0
 2004 Microchip Technology Inc.
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