PIC16F684-ISL

Manufacturer Part NumberPIC16F684-ISL
ManufacturerMicrochip Technology Inc.
PIC16F684-ISL datasheets
 

Specifications of PIC16F684-ISL

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PIC16F684
10.1
EECON1 and EECON2 Registers
EECON1 is the control register with four low-order bits
physically implemented. The upper four bits are non-
implemented and read as ‘0’s.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset during normal
operation. In these situations, following Reset, the user
REGISTER 10-3:
EECON1 – EEPROM CONTROL REGISTER (ADDRESS: 9Ch)
U-0
bit 7
bit 7-4
Unimplemented: Read as ‘0’
bit 3
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during
normal operation or BOD detect)
0 = The write operation completed
bit 2
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the data EEPROM
bit 1
WR: Write Control bit
1 = Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit
can only be set, not cleared, in software.)
0 = Write cycle to the data EEPROM is complete
bit 0
RD: Read Control bit
1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit
can only be set, not cleared, in software.)
0 = Does not initiate an EEPROM read
Legend:
S = Bit can only be set
R = Readable bit
-n = Value at POR
DS41202C-page 72
can check the WRERR bit, clear it and rewrite the
location. The data and address will be cleared. There-
fore, the EEDAT and EEADR registers will need to be
re-initialized.
Interrupt flag, EEIF bit (PIR1<7>), is set when write is
complete. This bit must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the data EEPROM write sequence.
Note:
The EECON1, EEDAT and EEADR
registers should not be modified during a
data EEPROM write (WR bit = 1).
U-0
U-0
U-0
R/W-x
WRERR
W = Writable bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
‘0’ = Bit is cleared
Preliminary
R/W-0
R/S-0
R/S-0
WREN
WR
RD
bit 0
x = Bit is unknown
 2004 Microchip Technology Inc.